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公开(公告)号：US20140040685A1
公开(公告)日：2014-02-06
申请号：US13567127
申请日：2012-08-06
IPC分类号： G11C29/12
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译： 本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。 在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。
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公开(公告)号：US08239818B1
公开(公告)日：2012-08-07
申请号：US13080055
申请日：2011-04-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14 , G11C29/12
摘要： A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.
摘要翻译： 可以在芯片设计平台内使用的系统和相关数据结构来定义MBIST架构的结构。 一种用于生成内置于自我测试（MBIST）设计文件中的内存的系统，包括用于处理组织文件（Org File）的工具，其中组织文件包括指定MBIST设计文件的结构并符合的代码行 到工具定义的数据结构; 其中所述数据结构提供基础设施以描述：在设计级别的MBIST组件之间的关联; MBIST组件与分级测试端口在设计级别之间的关联; 以及在设计级别的MBIST组件之间的菊花链的串行顺序。
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公开(公告)号：US08661399B1
公开(公告)日：2014-02-25
申请号：US13567127
申请日：2012-08-06
IPC分类号： G06F17/50
摘要： Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.
摘要翻译： 本发明的方面提供了用于为集成电路（IC）芯片创建内置自测（BIST）组织文件。 在一个实施例中，一种方法包括：接收包括存储器模块层级的设计文件，每个模块包括多个存储器包装器; 在BIST类型的每个层级的内存模块中扫描每个内存包装器; 基于层次级别和BIST类型创建存储器包装器的有序列表; 根据BIST类型添加一个BIST引擎，用于在有序列表中列出的每个内存包装器; 并将多个引用语句添加到有序列表以创建BIST组织文件。
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4.发明授权公开(公告)号：US08595678B2
公开(公告)日：2013-11-26
申请号：US13365370
申请日：2012-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译： 公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。 检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接 块和其他逻辑块。
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公开(公告)号：US20130205268A1
公开(公告)日：2013-08-08
申请号：US13365370
申请日：2012-02-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/14
摘要： Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.
摘要翻译： 公开了一种用于创建检查语句的程序，其可以随后用于验证电路设计中的逻辑块之间的互连。 检查语句是通过描述电路设计中的逻辑块如何相互关联（如果有的话）来创建的，并且将描述与对每个逻辑块特定的规则语句进行交叉引用，以定义特定逻辑之间的允许连接 块和其他逻辑块。
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6.发明授权Multi-valued or single strength signal detection in a hardware description language 有权硬件描述语言中的多值或单强度信号检测公开(公告)号：US07219316B2
公开(公告)日：2007-05-15
申请号：US10605747
申请日：2003-10-23
CPC分类号： G06F17/5022
摘要： A method, module, and program product for detecting signal strengths in a hardware description language, such as Verilog, that does not provide for such detection. The method includes the steps of creating a wired net configuration that provides for a data input signal and a controlled reference signal; varying the controlled reference signal based on a desired signal strength to be detected; and comparing the input signal with the controlled reference signal to determine if the desired signal strength has been detected.
摘要翻译： 一种用于检测硬件描述语言（例如Verilog）中不提供这种检测的信号强度的方法，模块和程序产品。 该方法包括创建提供数据输入信号和受控参考信号的有线网络配置的步骤; 基于要检测的期望信号强度改变受控参考信号; 以及将输入信号与受控参考信号进行比较，以确定是否检测到所需的信号强度。
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