公开(公告)号：US11200348B2

公开(公告)日：2021-12-14

申请号：US16663072

申请日：2019-10-24

Applicant: Cryptography Research, Inc

Inventor： Roberto Rivoir ,  Elke De Mulder ,  Jean-Michel Cioranesco

IPC: G06F21/75

Abstract: A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.

公开(公告)号：US20170061121A1

公开(公告)日：2017-03-02

申请号：US15245507

申请日：2016-08-24

Applicant: Cryptography Research, Inc

Inventor： Roberto Rivoir ,  Elke De Mulder ,  Jean-Michel Cioranesco

IPC: G06F21/55

CPC classification number: G06F21/755 ,  G06F2221/034

Abstract: A side-channel attack resistant circuit topology for performing logic functions. This topology includes combinatorial logic to perform the at least one logic function. A logic input selector alternately supplies, in response to a first timing reference signal, an input to the combinatorial logic with noise generating input values and valid input values. A first latch input selector alternately supplies, in response to the first timing reference signal, a first memory element input with noise generating input values and valid logic output values. The valid logic output values are received from the combinatorial logic. A first memory element latches the valid logic output values in response to a second timing reference signal.

Abstract translation: 用于执行逻辑功能的侧信道攻击电路拓扑。 该拓扑包括用于执行至少一个逻辑功能的组合逻辑。 逻辑输入选择器响应于第一定时参考信号交替地提供具有噪声产生输入值和有效输入值的组合逻辑的输入。 第一锁存器输入选择器响应于第一定时参考信号交替地提供输入噪声产生输入值和有效逻辑输出值的第一存储器元件。 从组合逻辑接收有效的逻辑输出值。 响应于第二定时参考信号，第一存储器元件锁存有效的逻辑输出值。