公开(公告)号：US20190007034A1

公开(公告)日：2019-01-03

申请号：US15980797

申请日：2018-05-16

Applicant: DENSO CORPORATION

Inventor： Satoshi NAKAI ,  Ippei KAWAMOTO

IPC: H03K5/1252 ,  H03K21/08 ,  G06F1/08

Abstract: A clock signal generator circuit includes a CR oscillator part, which outputs a clock signal having a frequency corresponding to a time constant determined by a capacitor and a resistor, and a frequency varying part. The frequency varying part includes a counter for performing a counting operation and varies a frequency of the clock signal by varying a resistance value of the resistor in correspondence to a count value of the counter. The resistor of the CR oscillator part includes plural resistive elements, one terminal of which are connected to a common node. The frequency varying part includes tri-state buffers, input terminals of which are connected in common and output terminals of which are connected to other terminals of the resistive elements, respectively, and varies the resistance value of the resistor by switching over states of the buffers in correspondence to the count value.