公开(公告)号：US20100199269A1

公开(公告)日：2010-08-05

申请号：US12668967

申请日：2008-10-08

申请人： Dai Hattori ,  Tomoo Hamada

发明人： Dai Hattori ,  Tomoo Hamada

IPC分类号： G06F9/45

CPC分类号： G06F8/443

摘要： A program optimization device which, when optimizing a program, performs optimization depending on characteristics of data to be processed by the program without having to execute the program before the optimization, includes: an intermediate code conversion unit that converts an input program to be optimized, into an intermediate code; a variable value setting unit that sets a possible value of a variable according to externally provided information; a node value calculation unit that calculates a possible value of a node included in the intermediate code according to the value set by the variable value setting unit; an intermediate code optimization unit that optimizes the intermediate code according to the value calculated by the node value calculation unit; and an output program conversion unit that converts the intermediate code optimized by the intermediate code optimization unit, to an output program.

摘要翻译： 一种程序优化装置，当优化程序时，根据程序要处理的数据的特性执行优化，而不必在优化之前执行程序，包括：中间代码转换单元，其转换要优化的输入程序， 成为中间代码 可变值设定单元，根据外部提供的信息设定变量的可能值; 节点值计算单元，根据由所述可变值设定单元设定的值，计算包含在所述中间代码中的节点的可能值; 中间代码优化单元，其根据由所述节点值计算单元计算出的值来优化所述中间代码; 以及输出程序转换单元，其将由中间代码优化单元优化的中间代码转换为输出程序。

公开(公告)号：US07194724B2

公开(公告)日：2007-03-20

申请号：US10991052

申请日：2004-11-16

申请人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

发明人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.

摘要翻译： 首先，计算在行为级别电路中描述的变量的引用次数。 接下来，提取变量的位宽，并且选择能够提取所提取的位宽度的数据传送的多个存储器。 接下来，基于参考的数量和变量的位宽来计算当分配了变量时的所选择的多个存储器中的每一个的存储器访问的频率的总和。 之后，作为用于分配变量的目标，选择最小化计算出的存储器访问频率之和的存储器。

公开(公告)号：US06925628B2

公开(公告)日：2005-08-02

申请号：US10690957

申请日：2003-10-21

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A high-level synthesis method of the present invention includes: generating a CDFG (Control Data Flow Graph) based an input file describing a behavior of a digital circuit; allocating each node of the CDFG generated in the CDFG generation, expressing contents of processing, to a time synchronized with a clock called a Step, based on the CDFG and a constraint condition of the digital circuit described in a constraint file, thereby scheduling the CDFG; generating allocation information representing how resources for constituting the digital circuit are allocated to respective nodes of the CDFG scheduled in the scheduling, based on resource-level layout information representing a layout of the resources, and circuit information representing a connecting relationship between the resources; and outputting the circuit information generated in the allocation and circuit information generation.

摘要翻译： 本发明的高级合成方法包括：基于描述数字电路的行为的输入文件生成CDFG（控制数据流图）; 基于CDFG和约束文件中描述的数字电路的约束条件，将表示处理内容的CDFG生成中生成的CDFG的每个节点分配到与称为步骤的时钟同步的时间，从而调度CDFG ; 基于表示资源布局的资源级布局信息，以及表示资源之间的连接关系的电路信息，生成表示如何将用于构成数字电路的资源分配给调度调度的CDFG的各个节点的分配信息; 并输出在分配和电路信息生成中产生的电路信息。

公开(公告)号：US08020136B2

公开(公告)日：2011-09-13

申请号：US12038740

申请日：2008-02-27

申请人： Dai Hattori ,  Keiichi Kurokawa

发明人： Dai Hattori ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A high-level synthesis unit creates a first register transfer level circuit from an operation level description. A circuit creating unit creates a second register transfer level circuit based on circuit information for creating an additional circuit to be added to the first register transfer level circuit. A circuit connecting unit connects the first register transfer level circuit with the second register transfer level circuit, based on connecting information describing a connecting relation between a signal in the first register transfer level circuit and a signal in the second register transfer level circuit.

摘要翻译： 高级合成单元从操作级别描述创建第一寄存器传送电平电路。 电路创建单元基于用于创建要添加到第一寄存器传送电平电路的附加电路的电路信息来创建第二寄存器传送电平电路。 电路连接单元基于描述第一寄存器传送电平电路中的信号与第二寄存器传送电平电路中的信号之间的连接关系的连接信息，将第一寄存器传送电平电路与第二寄存器传送电平电路连接。

公开(公告)号：US20070250803A1

公开(公告)日：2007-10-25

申请号：US11785800

申请日：2007-04-20

申请人： Dai Hattori ,  Keiichi Kurokawa ,  Yuichiro Ishikawa

发明人： Dai Hattori ,  Keiichi Kurokawa ,  Yuichiro Ishikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： The present invention generates a register transfer level description from a behavior description based on a result obtained by referring to a data path template wherein definition is given with respect to; a group of functional units where a generating method of a circuit in a register transfer level is defined; and a connection relationship of signals between each of functional units that constitute the group of functional units.

摘要翻译： 本发明基于通过参考其中给出定义的数据路径模板获得的结果，从行为描述生成寄存器传送级别描述; 一组功能单元，其中定义了寄存器传送级的电路的产生方法; 以及构成功能单元组的各功能单元之间的信号的连接关系。

公开(公告)号：US20050289499A1

公开(公告)日：2005-12-29

申请号：US11159291

申请日：2005-06-23

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

摘要翻译： 产生表示电路设计规范中的计算和数据流的曲线图CD1G，获得处理所需的时钟周期，从而生成分配的资源连接图。当分配的资源 连接图包括分配了具有相同功能的硬件资源的节点，在节点S103之间添加用于控制节点共享的共享边。提供具有添加了共享边的已分配资源连接图的临时布局S 104，并且基于布局结果S 105共享所分配的资源连接图的节点。共享边缘被赋予诸如吸引力或排斥性的属性或权重。 因此，控制布局结果中的节点之间的距离，并且控制资源共享的程度。

公开(公告)号：US07237220B2

公开(公告)日：2007-06-26

申请号：US11159291

申请日：2005-06-23

申请人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

发明人： Osamu Ogawa ,  Dai Hattori ,  Keiichi Kurokawa ,  Masahiko Toyonaga

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A CDFG which is a graph representing calculations and a data flow included in the design specifications of a circuit is generated S101, a clock cycle required for the processing is obtained and thus an allocated resource connection graph is generated S102. When the allocated resource connection graph includes nodes to which hardware resources having the same function are allocated, a sharing edge for controlling sharing of the nodes is added between the nodes S103. A provisional layout of the allocated resource connection graph having the sharing edge added thereto is provided S104, and the nodes of the allocated resource connection graph are shared based on the layout result S105. The sharing edge is provided with attribute or weight such as attraction or repulsion. Thus, the distance between the nodes in the layout result is controlled and the degree at which the resources are shared is controlled.

摘要翻译： 产生表示电路设计规范中的计算和数据流的曲线图CD1G，获得处理所需的时钟周期，从而生成分配的资源连接图。当分配的资源 连接图包括分配了具有相同功能的硬件资源的节点，在节点S103之间添加用于控制节点共享的共享边。提供具有添加了共享边的已分配资源连接图的临时布局S 104，并且基于布局结果S 105共享所分配的资源连接图的节点。共享边缘被赋予诸如吸引力或排斥性的属性或权重。 因此，控制布局结果中的节点之间的距离，并且控制资源共享的程度。

公开(公告)号：US20050125762A1

公开(公告)日：2005-06-09

申请号：US10991052

申请日：2004-11-16

申请人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

发明人： Dai Hattori ,  Osamu Ogawa ,  Keiichi Kurokawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.

摘要翻译： 首先，计算在行为级别电路中描述的变量的引用次数。 接下来，提取变量的位宽，并且选择能够提取所提取的位宽度的数据传送的多个存储器。 接下来，基于参考的数量和变量的位宽来计算当分配了变量时的所选择的多个存储器中的每一个的存储器访问的频率的总和。 之后，作为用于分配变量的目标，选择最小化计算出的存储器访问频率之和的存储器。