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公开(公告)号：US20060038587A1
公开(公告)日：2006-02-23
申请号：US11254577
申请日：2005-10-20
IPC分类号： H03K19/0175 , G06F13/00
CPC分类号： G06F13/4077 , H04L5/16
摘要： In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
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2.发明申请公开(公告)号：US20050146358A1
公开(公告)日：2005-07-07
申请号：US10752956
申请日：2004-01-07
IPC分类号： G06F13/40 , H03K19/094 , H04L5/16
CPC分类号： G06F13/4077 , H04L5/16
摘要： In a bi-directional, self-synchronous bus for communication between semiconductor devices, a logic delay is provided as a flag to a state machine control for indicating that the bus is making a transition from a low to a high state. The logic delay causes the bus to adaptively idle until the bus settles, making it amenable for a wide variety of bus sizes and topologies. In this way, oscillation of the bus is avoided without slowing the speed of the state machine clock.
摘要翻译： 在用于半导体器件之间的通信的双向自同步总线中，提供逻辑延迟作为状态机控制的标志，用于指示总线正在从低状态转变为高状态。 逻辑延迟导致总线自适应空闲，直到总线稳定，使其适用于各种总线大小和拓扑。 以这种方式，避免了总线的振荡，而不会降低状态机时钟的速度。
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3.发明申请公开(公告)号：US20050066065A1
公开(公告)日：2005-03-24
申请号：US10668488
申请日：2003-09-23
CPC分类号： H04L5/1423
摘要： A communication system for establishing bidirectional, asynchronous communication between a first device and a second device. The system includes first asynchronous encoder logic and second asynchronous encoder logic for controlling the state of the communication system such that bidirectional communication is enabled without a direction control line.
摘要翻译： 一种用于在第一设备和第二设备之间建立双向异步通信的通信系统。 该系统包括用于控制通信系统的状态的第一异步编码器逻辑和第二异步编码器逻辑，使得双向通信在没有方向控制线的情况下被启用。
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