公开(公告)号：US20110110171A1

公开(公告)日：2011-05-12

申请号：US12620365

申请日：2009-11-17

申请人： David A. KAMP ,  Filippo MARINELLI ,  Thierry ROZ

发明人： David A. KAMP ,  Filippo MARINELLI ,  Thierry ROZ

IPC分类号： G11C7/20

CPC分类号： E05B39/00

摘要： The external event detection device comprises an electronic unit (22) and an external event sensor (16), the electronic unit having at least a non-volatile memory cell (24, T1) in which data relative to at least one external event detected by the external event sensor can be stored. According to the invention, the external event sensor defines an energy harvester that transforms energy from said at least one external event into electrical energy contained in an electrical stimulus pulse provided to the electronic unit. The electronic unit is arranged for storing said data by using only the electrical energy contained in the electrical stimulus pulse. In particular, the non-volatile memory cell is directly set to its written logical state from its initial logical state by the electrical stimulus pulse provided by said energy harvester. In a preferred embodiment, the electronic unit further comprises a set circuit (26) comprising a second FET transistor (T2) arranged between the ground of the electronic unit and the drain of a first FET transistor (T1) defining the non-volatile memory cell, this switch having a control gate connected to the control gate of the first FET transistor. The second FET transistor is turned on when an electrical stimulus pulse is provided to the electronic unit, connecting the drain (DRN) of the first FET transistor (T1) to ground and thus allowing the secure setting of the non-volatile memory cell.

摘要翻译： 外部事件检测装置包括电子单元（22）和外部事件传感器（16），所述电子单元至少具有非易失性存储单元（24，T1），其中相对于由 可以存储外部事件传感器。 根据本发明，外部事件传感器限定能量收集器，其将来自所述至少一个外部事件的能量转换成提供给电子单元的电刺激脉冲中包含的电能。 电子单元被布置成通过仅使用包含在电刺激脉冲中的电能来存储所述数据。 特别地，非易失性存储单元通过由所述能量收集器提供的电刺激脉冲从其初始逻辑状态直接设置为其写入的逻辑状态。 在优选实施例中，电子单元还包括设置电路（26），其设置在第二FET晶体管（T2）之间，第二FET晶体管（T2）布置在电子单元的接地和限定非易失性存储单元的第一FET晶体管（T1）的漏极之间 该开关具有连接到第一FET晶体管的控制栅极的控制栅极。 当向电子单元提供电刺激脉冲时，第二FET晶体管导通，将第一FET晶体管（T1）的漏极（DRN）接地，从而允许非易失性存储单元的安全设置。