公开(公告)号：US5109495A

公开(公告)日：1992-04-28

申请号：US306843

申请日：1989-02-03

申请人： David B. Fite ,  Tryggve Fossum ,  William R. Grundmann ,  Dwight P. Manely ,  Francis X. McKeen ,  John E. Murray ,  Ronald M. Salett ,  Eileen Samberg ,  Daniel P. Stirling

发明人： David B. Fite ,  Tryggve Fossum ,  William R. Grundmann ,  Dwight P. Manely ,  Francis X. McKeen ,  John E. Murray ,  Ronald M. Salett ,  Eileen Samberg ,  Daniel P. Stirling

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3824 ,  G06F9/3867

摘要： To execute variable-length instructions independently of instruction preprocessing, a central processing unit is provided with a set of queues in the data and control paths between an instruction unit and an execution unit. The queues include a "fork" queue, a source queue, a destination queue, and a program counter queue. The fork queue contains an entry of control information for each instruction processed by the instruction unit. This control information corresponds to the opcode for the instruction, and preferably it is a microcode "fork" address at which a microcode execution unit begins execution to execute the instruction. The source queue specifies the source operands for the instruction. Preferably the source queue stores source pointers and the operands themselves are included in a separate "source list" in the case of operands fetched from memory or immediate data from the instruction stream, or are the contents of a set of general purpose registers in the execution unit. The destination queue specifies the destination for the instruction, for example, either memory or general purpose registers. The program counter queue contains the starting value of the program counter for each of the instructions passed from the instruction unit to the execution unit. Preferably the queues are large enough to hold control information and data for up to six instructions. The queues therefore shield the execution unit and the instruction unit from each others complexities and provide a buffer to allow for an uneven processing rate in either of them.