公开(公告)号：US6141259A

公开(公告)日：2000-10-31

申请号：US252409

申请日：1999-02-18

申请人： David B. Scott ,  Donald J. Coleman, deceased

发明人： David B. Scott ,  Donald J. Coleman, deceased

IPC分类号： G11C7/12 ,  G11C11/4094 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/12 ,  H01L27/10897

摘要： A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage. The p-channel transistors (P401 and P402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a minimum level of VSS+Vtp, where Vtp is the p-channel transistor threshold voltage. For dynamic RAM applications, memory cells having a higher charge storage capability are disclosed to compensate for the lower array voltages used during refresh operations.

摘要翻译： 公开了具有阵列工作电压双极性降低的随机存取存储器（RAM）。 在优选实施例中，钳位传输门电路（414）将成对的位线（BL和/ BL）耦合到感测节点对（410和412）。 钳位传输门电路414包括与将位线（BL或/ BL）耦合到感测节点（410）的p沟道MOS晶体管（P401和P402）串联的n沟道MOS晶体管（N401和N402） 或412）。 n沟道晶体管（N401和N402）的栅极由高电源电压（VDD）驱动，p沟道晶体管（P401和P402）的栅极由低电源电压（VSS）驱动， 。 感测放大器电路（418）将感测节点对（410和412）驱动到相反的电源电压（VDD和VSS）。 钳位传输门电路（414）中的n沟道晶体管（N401和N402）将位线（BL和/ BL）上的电压钳位到VDD-Vtn的最大电平，其中Vtn是n沟道晶体管阈值 电压。 钳位传输门电路（414）中的p沟道晶体管（P401和P402）将位线（BL和/ BL）上的电压钳位到VSS + Vtp的最小电平，其中Vtp是p沟道晶体管阈值 电压。 对于动态RAM应用，公开了具有较高电荷存储能力的存储器单元以补偿刷新操作期间使用的较低阵列电压。