公开(公告)号：US4991185A

公开(公告)日：1991-02-05

申请号：US460500

申请日：1990-01-03

申请人： David Hatten ,  Joe Foster ,  Walter Fry ,  Barry Drager ,  Abdul Rashid

发明人： David Hatten ,  Joe Foster ,  Walter Fry ,  Barry Drager ,  Abdul Rashid

IPC分类号： G01R31/3185

CPC分类号： G01R31/318527 ,  G06F2201/88

摘要： This invention relates to a method of testing an n-bit programmable counter. It is desired to test the n-bit programmable counter in fewer than 2.sup.n cycles. Accordingly, a counter value output on the counter is coupled to a variable increment rate input on the counter. Each bit of the counter is reset to a binary 0 initial state. A binary 1 state is loaded into a carry-in bit of the counter and the counter is iteratively doubled, by means of the coupling between the counter value output and the variable increment rate input, until a carry-out bit of the counter assumes the binary 1 state to thereby allow the counter to be fully tested in n+1 iterations. The counter value output and the variable increment rate input are decoupled from the counter when the counter is not being tested. The counter is provided with a parallel load input to allow simultaneous resetting of each bit. Intermediate counter values may be checked to provide a means for localizing errors within the counter.

摘要翻译： 本发明涉及一种测试n位可编程计数器的方法。 希望在少于2n个周期内测试n位可编程计数器。 因此，在计数器上输出的计数器值耦合到计数器上的可变增量率输入。 计数器的每一位复位为二进制0初始状态。 二进制1状态被加载到计数器的进位位，并且通过计数器值输出和可变增量率输入之间的耦合，计数器被迭代地加倍，直到计数器的进位位置为 二进制1状态，从而允许计数器在n + 1次迭代中被完全测试。 当计数器未被测试时，计数器值输出和可变增量率输入与计数器去耦。 该计数器具有并行负载输入，以允许同时复位每个位。 可以检查中间计数器值以提供用于在计数器内定位错误的手段。