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公开(公告)号：US07020675B2
公开(公告)日：2006-03-28
申请号：US10106736
申请日：2002-03-26
申请人： David J. Comer , Aaron K. Martin , James E. Jaussi
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistors groups, each of the transistor groups has a plurality of binary weighted transistor pairs. A select unit selects the binary weighted transistor pairs based on binary code signals so that each transistor pair passes a current from one of the source nodes to either a reference node or a summing node.
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公开(公告)号：US07010563B2
公开(公告)日：2006-03-07
申请号：US10106617
申请日：2002-03-26
申请人： David J. Comer , Aaron K. Martin , James E. Jaussi
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： A multiplier includes an input stage to receive input signals to provide currents at a plurality of source nodes. An output stage includes a plurality of transistor groups, each of the transistor groups includes a plurality of transistor pairs. The values of currents produced by the output stage can be controlled by selecting appropriate parameters of the transistor pairs.
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公开(公告)号：US06630818B1
公开(公告)日：2003-10-07
申请号：US10106757
申请日：2002-03-26
申请人： David J. Comer , Aaron K. Martin , James E. Jaussi
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G05F316
CPC分类号： G05F3/262
摘要： A current mirror includes an input node to receive an input current, an output node to produce an output current, and a reference node. The current mirror also includes a potential reduction unit to allow the voltage at the input node to be less than the voltage at the reference node.
摘要翻译： 电流镜包括用于接收输入电流的输入节点，产生输出电流的输出节点和参考节点。 电流镜还包括允许输入节点处的电压小于参考节点处的电压的电位减小单元。
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公开(公告)号：US06563369B1
公开(公告)日：2003-05-13
申请号：US10106565
申请日：2002-03-26
申请人： David J. Comer , Aaron K. Martin , James E. Jaussi
发明人： David J. Comer , Aaron K. Martin , James E. Jaussi
IPC分类号： G05F110
CPC分类号： G05F3/262
摘要： A current summing circuit includes an active cascode pair of transistors having a source-drain junction connected to a summing node to receive an input current at the source-drain junction to output an output current at a source of a transistor of the active cascode pair of transistors.
摘要翻译： 电流求和电路包括有源共源共栅晶体管，其具有连接到求和节点的源极 - 漏极结，以接收在源极 - 漏极结处的输入电流，以在源极 - 漏极结的晶体管的源极处输出输出电流， 晶体管。
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公开(公告)号：US20080181331A1
公开(公告)日：2008-07-31
申请号：US12077987
申请日：2008-03-24
申请人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
发明人： Bryan K. Casper , Shekhar Y. Borkar , Stephen R. Mooney , Aaron K. Martin , Joseph T. Kennedy , Matthew B. Haycock , James E. Jaussi
CPC分类号： H04L25/4917
摘要： A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.
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公开(公告)号：US06624688B2
公开(公告)日：2003-09-23
申请号：US10041677
申请日：2002-01-07
IPC分类号： H03F345
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。
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公开(公告)号：US07301391B2
公开(公告)日：2007-11-27
申请号：US11181380
申请日：2005-07-14
CPC分类号： G06G7/16 , H03H11/1213
摘要： A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.
摘要翻译： 可以用多个差分输入级和可变尾电流来实现电流求和FIR滤波器。 可变尾电流可用于适当地加权当前和以前的数字输入信号。 可以将差分晶体管对的加权输出相加以提供经滤波的输出信号。 可以利用可变电流源或通过调整差分晶体管对的相对宽度来有利地改变尾电流。 在其他实施例中，可以添加额外的差分对以调整由电路装置的结构中的过程引起的变化引起的系统偏移电压或引起期望的偏移。
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9.发明授权公开(公告)号：US07177288B2
公开(公告)日：2007-02-13
申请号：US09998008
申请日：2001-11-28
申请人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
发明人： Stephen R. Mooney , Aaron K. Martin , Matthew B. Haycock , Bryan K. Casper , Shekhar Y. Borkar , Joseph T. Kennedy , James E. Jaussi
IPC分类号： H04L5/14
CPC分类号： H04L5/1423
摘要： A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.
摘要翻译： 一种设备包括总线，连接到总线的第一发射机，并且被配置为在第一频带中通过总线传输第一信号，第二发射器连接到总线并且被配置为以第二频率通过总线发送第二信号 与第一发射机正在发送第一信号的同时，连接到总线并被配置为接收通过总线在第一频带中发送的第一信号的第一接收机和连接到总线的第二接收机，并且被配置为 接收在第二频带中通过总线发送的第二信号。 第一频带和第二频带占据频谱的不同部分。
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公开(公告)号：US06621323B1
公开(公告)日：2003-09-16
申请号：US10131443
申请日：2002-04-24
IPC分类号： H03K1730
CPC分类号： H04L25/0292 , G11C27/024 , H04L5/1423 , H04L25/0272 , H04L25/028
摘要： A circuit samples a voltage on a simultaneous bi-directional bus, and subtracts an outbound voltage to determine an inbound voltage. Sampling capacitors are variable to adjust for matching time constants. A mechanism is provided to sample error voltages over clock phase variations and sampling capacitor values.
摘要翻译： 电路对同时双向总线上的电压进行采样，并减去出站电压以确定入站电压。 采样电容是可变的，用于调整匹配的时间常数。 提供了一种机制来对时钟相位变化和采样电容值进行误差电压的采样。
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