专利检索 ap:("David M. Pini" OR "Yuefei Ge" OR "Anup S. Tirumala") AND inv:"David M. Pini" 第 1 页

1.

发明授权
Sign generation bypass path to aligner for reducing signed data load latency 有权
标题翻译：标记生成旁路路径到对齐器，以减少带符号的数据加载延迟

公开(公告)号：US06965985B2

公开(公告)日：2005-11-15

申请号：US09994479

申请日：2001-11-27

申请人： David M. Pini , Yuefei Ge , Anup S. Tirumala

发明人： David M. Pini , Yuefei Ge , Anup S. Tirumala

IPC分类号： G06F9/00 , G06F9/302 , G06F9/312

CPC分类号： G06F9/30043 , G06F9/30014

摘要： A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.

摘要翻译： 已经开发了一种用于减少微处理器中的签名负载延迟的方法。该方法包括通过旁路将一部分数据传送到对准器，并从数据的一部分生成符号位。符号位沿着旁路传送到对准器，数据沿数据通路单独传送到对准器。