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公开(公告)号：US08456885B2
公开(公告)日：2013-06-04
申请号：US12535261
申请日：2009-08-04
申请人： Derek Tolmie , Arnaud Laflaquiere , Francois Roy
发明人： Derek Tolmie , Arnaud Laflaquiere , Francois Roy
IPC分类号： G11C11/36
CPC分类号： G11C13/04 , H01L27/14609 , H04N5/335 , H04N5/37452 , H04N5/37457
摘要： A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.
摘要翻译： 随机存取存储器电路包括多个像素，每个像素具有光敏区域和在至少每个光敏区域上布置的遮光层。 在替代实施例中，电路包括用于存储数据的多个存储元件。 每个存储元件可以包括形成在具有布置在光电二极管上的光的光电二极管之间的位节点和可以存储数据的开关元件。 电路还可以包括用于从存储器单元读取和写入数据的多个读取和写入电路。
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公开(公告)号：US20100061139A1
公开(公告)日：2010-03-11
申请号：US12535261
申请日：2009-08-04
申请人： Derek Tolmie , Arnaud Laflaquiere , Francois Roy
发明人： Derek Tolmie , Arnaud Laflaquiere , Francois Roy
CPC分类号： G11C13/04 , H01L27/14609 , H04N5/335 , H04N5/37452 , H04N5/37457
摘要： A random access memory circuit includes a plurality of pixels, each having a light sensitive area and a light blocking layer arranged over at least each of the light sensitive areas. In an alternative embodiment, the circuit includes a plurality of memory elements for storing data. Each memory element may comprise a bit node formed between a photodiode, having a light arranged over the photodiode, and a switching element, where data may be stored. The circuit may also include a plurality of reading and writing circuits for reading and writing data to and from the memory cells.
摘要翻译： 随机存取存储器电路包括多个像素，每个像素具有光敏区域和在至少每个光敏区域上布置的遮光层。 在替代实施例中，电路包括用于存储数据的多个存储元件。 每个存储元件可以包括形成在具有布置在光电二极管上的光的光电二极管之间的位节点和可以存储数据的开关元件。 电路还可以包括用于从存储器单元读取和写入数据的多个读取和写入电路。
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公开(公告)号：US08772695B2
公开(公告)日：2014-07-08
申请号：US13324009
申请日：2011-12-13
摘要： Each column of pixels in an image sensor array has at least two column bitlines connected to an output of each pixel. A readout input circuit includes first inputs and a second input. Each first input is connected, via a capacitance, to a comparator input node. The second input is connected via a capacitance to the same comparator input node. The first inputs receive, in parallel, an analog signal acquired from the pixels via the column bitlines. The analog signals vary during a pixel readout period and have a first level during a first calibration period and a second level during a second read period with the analog signals being constantly read onto the capacitances during both the first calibration period and the second read period. The comparator compares an average of the signals on the plurality of first inputs to the reference signal.
摘要翻译： 图像传感器阵列中的每列像素具有连接到每个像素的输出的至少两列列位线。 读出输入电路包括第一输入和第二输入。 每个第一输入通过电容连接到比较器输入节点。 第二个输入通过电容连接到同一个比较器输入节点。 第一输入并行地接收通过列位线从像素获取的模拟信号。 模拟信号在像素读出周期期间变化，并且在第一校准周期期间具有第一电平，并且在第二读取周期期间具有第二电平，同时在第一校准周期和第二读取周期期间模拟信号恒定地读取到电容上。 比较器将多个第一输入端的信号的平均值与参考信号进行比较。
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公开(公告)号：US08305474B2
公开(公告)日：2012-11-06
申请号：US12622373
申请日：2009-11-19
申请人： Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachimi , Laurent Simony , Min Qu
发明人： Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachimi , Laurent Simony , Min Qu
CPC分类号： H04N5/3355 , H04N5/3577
摘要： An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.
摘要翻译： 图像传感器具有包括允许比较器电路执行相关双重采样的第一和第二电容器的每列ADC布置。 电容器分别连续地连接到模拟像素信号和斜坡信号，而不使用保持操作。 比较器电路包括差分输入端，连接到两个电容器的结，并被参考信号偏置。 参考信号优选地从参考电压采样和保持。 使用差分输入作为比较器的第一级，当大像素阵列以低对比度的场景成像时，可以解决地电压反弹引起的问题。 差分输入级的连接允许斜坡信号看到恒定的电容性负载，从而减少称为污迹的图像伪影。
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公开(公告)号：US20100157035A1
公开(公告)日：2010-06-24
申请号：US12622373
申请日：2009-11-19
申请人： Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachim , Laurent Simony , Min Qu
发明人： Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachim , Laurent Simony , Min Qu
CPC分类号： H04N5/3355 , H04N5/3577
摘要： An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.
摘要翻译： 图像传感器具有包括允许比较器电路执行相关双重采样的第一和第二电容器的每列ADC布置。 电容器分别连续地连接到模拟像素信号和斜坡信号，而不使用保持操作。 比较器电路包括差分输入端，连接到两个电容器的结，并被参考信号偏置。 参考信号优选地从参考电压采样和保持。 使用差分输入作为比较器的第一级，当大像素阵列以低对比度的场景成像时，可以解决地电压反弹引起的问题。 差分输入级的连接允许斜坡信号看到恒定的电容性负载，从而减少称为污迹的图像伪影。
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