公开(公告)号：US20190058399A1

公开(公告)日：2019-02-21

申请号：US16166262

申请日：2018-10-22

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Mark Childs ,  Tiago Patrao ,  Pietro Gallina ,  Alexandre Tavares ,  Michele De Fazio

IPC: H02M3/158 ,  H02M3/156 ,  H02M1/44

CPC classification number: H02M3/158 ,  H02M1/44 ,  H02M3/156

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

公开(公告)号：US10110126B2

公开(公告)日：2018-10-23

申请号：US14845381

申请日：2015-09-04

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Mark Childs ,  Tiago Patrao ,  Pietro Gallina ,  Alexandre Tavares ,  Michele De Fazio

IPC: H02M3/158 ,  H02M1/44 ,  H02M3/156

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

公开(公告)号：US20170070145A1

公开(公告)日：2017-03-09

申请号：US14845381

申请日：2015-09-04

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Mark Childs ,  Tiago Patrao ,  Pietro Gallina ,  Alexandre Tavares ,  Michele De Fazio

IPC: H02M3/158 ,  H03M1/66 ,  H02M1/44

CPC classification number: H02M3/158 ,  H02M1/44 ,  H02M3/156

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.

Abstract translation: 一种提供开关调节的电路和方法，被配置为提供具有降低的电磁干扰（EMI）的脉冲频率调制（PFM）操作模式，所述电磁干扰（EMI）包括输出级，所述输出级被配置为提供包括第一和第二晶体管的开关，感测电路， 从输出级的信息感测和电流限制参考，被配置为向电流限制基准提供信号的第一数模转换器（DAC），被配置为向第一数模转换器提供信号的加法器功能 （DAC）和线性移位反馈寄存器（LSFR），其被配置为向第一数模转换器（DAC）之后的加法器功能提供信号，并且LSFR从所述输出级接收时钟信号。

公开(公告)号：US10355595B2

公开(公告)日：2019-07-16

申请号：US16166262

申请日：2018-10-22

Applicant: Dialog Semiconductor (UK) Limited

Inventor： Mark Childs ,  Tiago Patrao ,  Pietro Gallina ,  Alexandre Tavares ,  Michele De Fazio

IPC: H02M3/158 ,  H02M1/44 ,  H02M3/156

Abstract: A circuit and method providing switching regulation configured to provide a pulse frequency modulation (PFM) mode of Operation with reduced electromagnetic interference (EMI) comprising an output stage configured to provide switching comprising a first and second transistor, a sense circuit configured to provide output current information sensing from an output stage and a current limit reference, a first digital-to-analog converter (DAC) configured to provide signal to the current limit reference, an adder function configured to provide a signal to the first digital-to-analog converter (DAC), and a linear shift feedback register (LSFR) configured to provide a signal to an adder function followed by the first digital-to-analog converter (DAC), and the LSFR receives a clock signal from said output stage.