公开(公告)号：US07180384B2

公开(公告)日：2007-02-20

申请号：US11136012

申请日：2005-05-23

申请人： Dimitrios Efstathiou ,  Ken Gentile

发明人： Dimitrios Efstathiou ,  Ken Gentile

IPC分类号： H03K7/00

CPC分类号： H04L27/362 ,  H04L27/361

摘要： Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

摘要翻译： 示出了通用信号调制器结构，其特别适用于从输入相位和幅度符号选择性地产生极调调制数字序列，并且用于从输入的第一和第二正交符号产生正交调制的数字序列。 重要的是，通过简单地改变模式命令的状态来选择这些实施例的调制结构（正交调制或极坐标调制）。

公开(公告)号：US20060261907A1

公开(公告)日：2006-11-23

申请号：US11136012

申请日：2005-05-23

申请人： Dimitrios Efstathiou ,  Ken Gentile

发明人： Dimitrios Efstathiou ,  Ken Gentile

IPC分类号： H03K7/00

CPC分类号： H04L27/362 ,  H04L27/361

摘要： Universal signal modulators structures are shown which are particularly useful for selectively generating polar-modulated digital sequences from input phase and amplitude symbols and for generating quadrature-modulated digital sequences from input first and second quadrature symbols. Significantly, the modulation structure (quadrature modulation or polar modulation) of these embodiments can selected by simply changing the state of a mode command.

摘要翻译： 示出了通用信号调制器结构，其特别适用于从输入相位和幅度符号选择性地产生极调调制数字序列，并且用于从输入的第一和第二正交符号产生正交调制的数字序列。 重要的是，通过简单地改变模式命令的状态来选择这些实施例的调制结构（正交调制或极坐标调制）。

公开(公告)号：US07248646B1

公开(公告)日：2007-07-24

申请号：US10126258

申请日：2002-04-19

申请人： Dimitrios Efstathiou

发明人： Dimitrios Efstathiou

IPC分类号： H04L27/20 ,  H03K5/159

CPC分类号： H04L25/03834

摘要： A reconfigurable communication transmitter core includes a digital pulse-shaping filter to perform pulse-shaping operations upon a digital modulated signal and a finite state machine to controls operation and reconfiguration of the digital pulse-shaping filter. A first memory stores coefficients and a second memory stores data. A multiplier multiplies a data value stored in the second memory with a corresponding coefficient value stored in the first memory. An adder adds each multiplication product from the multiplier with the content of an accumulation register wherein the accumulation register accumulates the sum from the adder. A rounding unit rounds off the content of the accumulation register and to provide rounded-off content as an output of the reconfigurable communication transmitter core. The finite state machine reconfigures a look-up table value set in the first memory, the first memory having pre-stored therein pulse shaped filtered waveforms. The pulse shaped filtered waveform having been pre-calculated.

摘要翻译： 可重新配置的通信发射机核心包括数字脉冲整形滤波器，用于对数字调制信号执行脉冲整形操作和有限状态机以控制数字脉冲整形滤波器的操作和重新配置。 第一存储器存储系数，第二存储器存储数据。 乘法器将存储在第二存储器中的数据值与存储在第一存储器中的相应系数值相乘。 加法器将来自乘法器的乘法乘积与累加寄存器的内容相加，其中累加寄存器从加法器累加和。 四舍五入单元舍弃累积寄存器的内容，并提供四舍五入的内容作为可重新配置的通信发射机核心的输出。 有限状态机重新配置在第一存储器中设置的查找表值，第一存储器预先存储有脉冲形滤波波形。 脉冲形滤波波形已被预先计算。

公开(公告)号：US06504867B1

公开(公告)日：2003-01-07

申请号：US09277263

申请日：1999-03-26

申请人： Dimitrios Efstathiou

发明人： Dimitrios Efstathiou

IPC分类号： H04B1700

CPC分类号： H04L27/2273 ,  H04L2027/0057

摘要： A digital radio tuner signal estimator receives a digitized in-phase (I) data signal and a digitized quadrature (Q) data signal and provides an estimated amplitude gain signal and an estimated signal-to-noise ratio signal value. The signal estimator includes a symmetrical matched I data digital filter having a first I filter section that filters the received I data signal and provides a first I data signal, and a second I filter section that filters the I data signal and provides a second I data signal. The signal estimator also includes a symmetrical matched Q data digital filter having a first Q filter section that filters the received Q data signal and provides a first Q data signal, and a second Q filter section that filters the Q data signal and provides a second Q data signal. The first and second I data signals and the first and second Q data signals are processed to compute an estimated amplitude gain. In addition, the first and second I data signals and the first and second Q data signals are processed to compute the estimated signal-to-noise ratio value. The present invention utilizes the symmetry of the FIR matched filter to facilitate providing signal estimation in a digital receiver.

摘要翻译： 数字无线电调谐器信号估计器接收数字化的同相（I）数据信号和数字化正交（Q）数据信号，并提供估计的振幅增益信号和估计的信噪比信号值。 信号估计器包括对称匹配的I数字数字滤波器，该数字滤波器具有对所接收的I数据信号进行滤波并提供第一I数据信号的第一I滤波器部分，以及对I数据信号进行滤波并提供第二I数据的第二I滤波器部分 信号。 信号估计器还包括对称的匹配Q数据滤波器，其具有滤波接收的Q数据信号并提供第一Q数据信号的第一Q滤波器部分和对Q数据信号进行滤波并提供第二Q信号的第二Q滤波器部分 数据信号。 处理第一和第二I数据信号以及第一和第二Q数据信号以计算估计的幅度增益。 此外，处理第一和第二I数据信号以及第一和第二Q数据信号以计算估计的信噪比值。 本发明利用FIR匹配滤波器的对称性便于在数字接收机中提供信号估计。

公开(公告)号：US06404825B1

公开(公告)日：2002-06-11

申请号：US09275210

申请日：1999-03-24

申请人： Dimitrios Efstathiou

发明人： Dimitrios Efstathiou

IPC分类号： H04L2714

CPC分类号： H04L27/34 ,  H04L2027/0028 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0073

摘要： A digital radio tuner lock detector receives an in-phase (I) data signal and a quadrature (Q) data signal. The lock detector processes these signals to compute a data signal power estimate and integrates the data signal power estimate to provide a threshold signal value. The lock detector also includes a carrier frequency lock detector and a carrier phase lock detector. The carrier frequency lock detector receives the I and Q data signals and computes a frequency error signal and integrates the frequency error signal to provide an integrated frequency error signal. The carrier frequency lock detector compares the magnitude of the integrated frequency error signal to the threshold signal value to determine if frequency lock has been achieved and provides a frequency lock status signal indicative thereof. The carrier phase lock detector receives the I and Q data signals and computes a phase error signal and integrates the phase error signal to provide an integrated phase error signal. The phase lock detector also compares the magnitude of the integrated phase error signal to the threshold signal value to determine if carrier phase lock has been achieved. Carrier frequency recovery occurs first and when the carrier frequency lock detector identifies carrier frequency lock, carrier phase recovery is then performed. Once the carrier phase lock detector identifies phase lock, then accurately received data is available for signal processing. The detector may be employed in either full digital demodulators (i.e., parameter estimation and correction are performed digitally) or hybrid demodulators (i.e., parameter estimation is performed digitally and carrier frequency and phase correction are performed in the continuous time domain).

摘要翻译： 数字无线电调谐器锁定检测器接收同相（I）数据信号和正交（Q）数据信号。 锁定检测器处理这些信号以计算数据信号功率估计，并且对数据信号功率估计进行积分以提供阈值信号值。 锁定检测器还包括载波频率锁定检测器和载波锁相检测器。 载波频率锁定检测器接收I和Q数据信号并计算频率误差信号，并对频率误差信号进行积分以提供积分频率误差信号。 载波频率锁定检测器将积分频率误差信号的幅度与阈值信号值进行比较，以确定是否已经实现频率锁定，并提供指示频率锁定状态信号。 载波相位锁定检测器接收I和Q数据信号，并计算相位误差信号，并对相位误差信号进行积分以提供积分相位误差信号。 锁相检测器还将积分相位误差信号的幅度与阈值信号值进行比较，以确定是否实现了载波相位锁定。 首先发生载波频率恢复，当载波频率锁定检测器识别载波频率锁定时，执行载波相位恢复。 一旦载波锁相检测器识别相位锁定，则准确接收的数据可用于信号处理。 检测器可以用于全数字解调器（即，数字地进行参数估计和校正）或混合解调器（即，以数字方式执行参数估计，并且在连续时域中执行载波频率和相位校正）。