Memory selftest method and apparatus same
    1.
    发明授权
    Memory selftest method and apparatus same 失效
    内存自适应方法和装置相同

    公开(公告)号:US5033048A

    公开(公告)日:1991-07-16

    申请号:US525203

    申请日:1990-04-19

    IPC分类号: G11C29/20 G11C29/36 G11C29/44

    CPC分类号: G11C29/44 G11C29/20 G11C29/36

    摘要: A method and apparatus for testing each memory location of a memory device, the method comprising the steps of: generating each of the memory addresses corresponding to each memory location in a pseudo-random order; generating a pseudo-random series of data words; storing one of the data words at each memory location; reading each data word back from memory; regenerating the series of data words; and comparing each read data word to the corresponding regenerated data word. The invention features generating and storing a second series of data words, each data word being inverse of the data words in the first series. The second series of data words are read from memory and compared to regenerated data. The invention also features a novel linear feedback shift register for generating the pseudo-random memory addresses and can generate the address zero. An accumulating register is utilized to store the approximate location of malfunctioning memory locations.

    摘要翻译: 一种用于测试存储器件的每个存储器位置的方法和装置,所述方法包括以下步骤:以伪随机顺序产生与每个存储器位置对应的每个存储器地址; 产生伪随机数据字串; 在每个存储器位置存储数据字中的一个; 从内存中读取每个数据字; 再生一系列数据字; 以及将每个读取的数据字与相应的再生数据字进行比较。 本发明的特征在于生成和存储第二系列数据字,每个数据字与第一系列中的数据字相反。 从存储器读取第二系列数据字,并与再生数据进行比较。 本发明还具有用于产生伪随机存储器地址并且可以生成地址零的新颖的线性反馈移位寄存器。 使用累加寄存器来存储故障存储器位置的大致位置。