公开(公告)号：US4710871A

公开(公告)日：1987-12-01

申请号：US438105

申请日：1982-11-01

申请人： William M. Belknap ,  Albert J. Chanasyk ,  Robert R. O'Dell ,  Donald J. Girard

发明人： William M. Belknap ,  Albert J. Chanasyk ,  Robert R. O'Dell ,  Donald J. Girard

IPC分类号： H04L1/00 ,  H04L1/16 ,  H04L1/18 ,  H04L12/413 ,  G06F13/00

CPC分类号： H04L1/1671 ,  H04L1/187 ,  H04L12/403 ,  H04L12/413 ,  H04L1/1874 ,  H04L2001/0093

摘要： A system for controlling the transfer of a data message over a common communication channel between a plurality of processing devices includes a MOS/LSI controller chip associated with each processing unit for constructing a message to be sent to a sending device acknowledging the receipt of the message and the validity of the message. Logic circuits are included which generate a predetermined sequence of two binary bits indicating the receipt of the message and the validity of the receiving message. The binary bits are framed by two other binary bits and the sequence repeated a predetermined number of times to construct an acknowledgment message. The controller chip further includes logic circuits for decoding the acknowledgment message.

摘要翻译： 用于控制在多个处理装置之间的公共通信信道上的数据消息的传送的系统包括与每个处理单元相关联的MOS / LSI控制器芯片，用于构造要发送到确认接收到该消息的发送设备的消息 和消息的有效性。 包括逻辑电路，其产生指示消息的接收和接收消息的有效性的两个二进制位的预定序列。 二进制位由两个其他二进制位构成，并且序列重复预定次数以构建确认消息。 控制器芯片还包括用于解码确认消息的逻辑电路。

公开(公告)号：US4466058A

公开(公告)日：1984-08-14

申请号：US308744

申请日：1981-10-02

申请人： Donald J. Girard ,  Robert R. O'Dell ,  Albert J. Chanasyk ,  William M. Belknap

发明人： Donald J. Girard ,  Robert R. O'Dell ,  Albert J. Chanasyk ,  William M. Belknap

IPC分类号： H04L29/00 ,  G06F13/00 ,  G06F13/374 ,  G06F3/00 ,  G06F9/46

CPC分类号： G06F13/374

摘要： A system for controlling the flow of data over a common bus between a plurality of processing units is disclosed which preferably includes a MOS/LSI circuit controller chip associated with each processing unit for awarding priority of access to the common bus when two or more processing units attempt to simultaneously gain access to the common bus. A contention circuit located in each controller chip is responsive to the sensing of each bit in the address of its associated processing unit, and generates a plurality of transitions on the common bus during the time a binary one bit is sensed in the address and listens for the presence of any transition on the common bus during the time a binary zero is sensed in the address. Access to the common bus is lost when transitions are detected on the bus during the time a binary zero bit is sensed and acquired when no transitions have been detected at the completion of the sensing of the address of the requesting processing unit.

摘要翻译： 公开了一种用于在多个处理单元之间通过公共总线控制数据流的系统，其优选地包括与每个处理单元相关联的MOS / LSI电路控制器芯片，用于当两个或更多个处理单元授予对公共总线的访问的优先级 尝试同时访问公共总线。 位于每个控制器芯片中的争用电路响应于其相关联的处理单元的地址中的每个位的感测，并且在地址中感测到二进制一位的时间内在公共总线上产生多个转换，并且侦听 在地址中检测到二进制零时，在公共总线上存在任何转换。 在检测到二进制零位并且在完成对请求处理单元的地址的检测完成时没有检测到转换时，在总线上检测到转换时，对公共总线的访问将丢失。