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公开(公告)号：US5732106A
公开(公告)日：1998-03-24
申请号：US465444
申请日：1995-06-05
CPC分类号： H04L25/03834
摘要： Disclosed is a digital pulse shaping circuit for reducing undesirable frequency components in subsequent data modulated transmissions, which circuit can be easily manufactured as a monolithic integrated circuit. In a preferred embodiment, the pulse shaping circuit employs an edge detector circuit to detect data transitions of an incoming serial data stream. Upon a data edge detection, the edge detector provides a control signal to a digital counter to enable the counter to begin counting applied clock pulses and generate a linear count. The linear count is provided to a decoding circuit, which generates an output word as a nonlinear function of the value of the count. The decoded output word then drives a digital modulator which modulates an RF carrier to provide wireless data transmission with improved spectral efficiency.
摘要翻译： 公开了一种数字脉冲整形电路，用于减少随后的数据调制传输中的不期望的频率分量，该电路可以容易地制造为单片集成电路。 在优选实施例中，脉冲整形电路采用边缘检测器电路来检测输入的串行数据流的数据转换。 在进行数据边缘检测时，边缘检测器向数字计数器提供控制信号，使计数器能够开始计数施加的时钟脉冲并产生线性计数。 将线性计数提供给解码电路，该解码电路产生输出字作为计数值的非线性函数。 解码的输出字然后驱动数字调制器，其调制RF载波以提供具有改进的频谱效率的无线数据传输。
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2.发明授权公开(公告)号：US07292067B2
公开(公告)日：2007-11-06
申请号：US11128424
申请日：2005-05-13
申请人： Daniel J. Schwarz
发明人： Daniel J. Schwarz
IPC分类号： H03K19/094
CPC分类号： H03K19/01759
摘要： A buffer system includes a logic adjusting circuit for translating a first logic level of a first component to a second logic level of a second component. The first and second logic level values are substantially different, and the buffer system has no directional control signal. A method of interfacing at least two components with different logic voltage requirements on a single bus without a separate directional control signal includes initializing a buffering circuit, activating the buffering circuit, transferring data through the buffering circuit, and deactivating the buffering circuit. A method of implementing a bi-directional interface between at least two devices interfaced on a bus includes providing a plurality of logic components interconnected to transfer data through the bus, and transferring data through the bus from a first device to a second device. The direction of data transfer is determined without a separate directional control signal.
摘要翻译： 缓冲器系统包括用于将第一组件的第一逻辑电平转换为第二组件的第二逻辑电平的逻辑调整电路。 第一和第二逻辑电平值基本上不同，并且缓冲器系统没有方向控制信号。 在单个总线上连接具有不同逻辑电压要求的至少两个组件的方法，无需单独的方向控制信号，包括初始化缓冲电路，激活缓冲电路，通过缓冲电路传输数据，以及停用缓冲电路。 实现在总线上接口的至少两个设备之间的双向接口的方法包括提供多个逻辑组件，互连以通过总线传送数据，以及通过总线将数据从第一设备传送到第二设备。 在没有单独的方向控制信号的情况下确定数据传送的方向。
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公开(公告)号：US20110091845A1
公开(公告)日：2011-04-21
申请号：US12840278
申请日：2010-07-20
IPC分类号： G09B19/00
摘要： The present invention provides systems and associated user interfaces that allow a service provider to manage predetermined aspects of one or more organization and utilize common aspects of plural managed organizations to advantageously utilize economies of scale associated with such common aspects and provide more efficient management of such organizations.
摘要翻译： 本发明提供了系统和相关联的用户界面，其允许服务提供商管理一个或多个组织的预定方面并且利用多个被管理组织的共同方面来有利地利用与这些共同方面相关联的规模经济并提供这种组织的更有效的管理 。
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