公开(公告)号：US11709795B2

公开(公告)日：2023-07-25

申请号：US17525146

申请日：2021-11-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jaehoon Chung

IPC: G06F15/80 ,  G06F1/10 ,  G06F9/30

CPC classification number: G06F15/8046 ,  G06F1/10 ,  G06F9/3017

Abstract: Disclosed is an electronic device which includes a main processor, and a systolic array processor, and the systolic array processor includes processing elements, a kernel data memory that provides a kernel data set to the processing elements, a data memory that provides an input data set to the processing elements, and a controller that provides commands to the processing elements. The main processor translates source codes associated with the systolic array processor into commands of the systolic array processor, calculates a switching activity value based on the commands, and stores the translated commands and the switching activity value to a machine learning module, which is based on the systolic array processor.

公开(公告)号：US11507429B2

公开(公告)日：2022-11-22

申请号：US16038243

申请日：2018-07-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chun-Gi Lyuh ,  Young-Su Kwon ,  Chan Kim ,  Hyun Mi Kim ,  Jeongmin Yang ,  Jaehoon Chung ,  Yong Cheol Peter Cho

IPC: G06N3/063 ,  G06F15/80 ,  G06F9/50 ,  G06N5/04 ,  G06F9/38 ,  G06F9/30

Abstract: Provided is a neural network accelerator which performs a calculation of a neural network provided with layers, the neural network accelerator including a kernel memory configured to store kernel data related to a filter, a feature map memory configured to store feature map data which are outputs of the layers, and a Processing Element (PE) array including PEs arranged along first and second directions, wherein each of the PEs performs a calculation using the feature map data transmitted in the first direction from the feature map memory and the kernel data transmitted in the second direction from the kernel memory, and transmits a calculation result to the feature map memory in a third direction opposite to the first direction.

公开(公告)号：US12210952B2

公开(公告)日：2025-01-28

申请号：US16201871

申请日：2018-11-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-Su Kwon ,  Chan Kim ,  Hyun Mi Kim ,  Jeongmin Yang ,  Chun-Gi Lyuh ,  Jaehoon Chung ,  Yong Cheol Peter Cho

IPC: G06N3/04

Abstract: A reorganizable neural network computing device is provided. The computing device includes a data processing array unit including a plurality of operators disposed at locations corresponding to a row and a column. One or more chaining paths which transfer the first input data from the operator of the first row of the data processing array to the operator of the second row are optionally formed. The plurality of first data input processors of the computing device transfer the first input data for a layer of the neural network to the operators along rows of the data processing array unit, and the plurality of second data input processors of the computing device transfer the second input data to the operators along the columns of the data processing array.