公开(公告)号：US20180189032A1

公开(公告)日：2018-07-05

申请号：US15394968

申请日：2016-12-30

申请人： ERIKO NURVITADHI ,  YU WANG ,  DEBORAH T. MARR

发明人： ERIKO NURVITADHI ,  YU WANG ,  DEBORAH T. MARR

IPC分类号： G06F9/44

CPC分类号： G06F8/20 ,  G06F8/30 ,  G06F17/5045 ,  G06F2217/08

摘要： An apparatus and method are described for designing an accelerator for processing sparse data. For example, one embodiment comprises a machine-readable medium having program code stored thereon which, when executed by a processor, causes the processor to perform the operations of: analyzing input graph program code and parameters associated with a target accelerator in view of an accelerator architecture template; responsively mapping the parameters onto the architecture template to implement customizations to the accelerator architecture template; and generating a hardware description representation of the target accelerator based on the determined mapping of the parameters to apply to the accelerator architecture template.