公开(公告)号：US20240281647A1

公开(公告)日：2024-08-22

申请号：US18570029

申请日：2022-06-13

申请人： ETH Zürich

发明人： Alexander Marc E. Meulemans ,  Benjamin Friedrich Grewe ,  Matilde Tristany Farinha ,  Javier Garcia Ordonez ,  Joao Rodrigues Sacramento ,  Pau Aceituno

IPC分类号： G06N3/065 ,  G06N3/0442

CPC分类号： G06N3/065 ,  G06N3/0442

摘要： The present invention relates to a time-continuous neural network circuit implemented on analog hardware with device mismatch, the circuit including a control unit (40) which is individually connected to each respective neuron of the circuit, the neurons in the hidden and output layers comprising a forward compartment for processing signals coming from preceding layers, a feedback compartment for processing feedback signals coming from the control unit and a central compartment for generating and sending a signal to the next layer or to the control unit. The control unit generates and sends to the feedback compartment of each respective neuron a feedback signal (Sf) based on the comparison between a network output signal (Sout) and a target signal (Star).