公开(公告)号：US11323082B2

公开(公告)日：2022-05-03

申请号：US16988727

申请日：2020-08-10

申请人： Elite Semiconductor Microelectronics Technology Inc.

发明人： Yang-Jing Huang ,  Shao-Ming Sun ,  Jhe-Jia Jhang

IPC分类号： H03F3/217 ,  H03F1/26 ,  H03F3/187 ,  H03F3/45

摘要： A class-D amplifier configured to adjust at least one input signal to at least one output signal. The class-D amplifier comprises: a loop filter, configured to receive the input signal; a PWM circuit, configured to generate at least one PWM signal; a summing circuit, coupled between an output of the loop filter and an input of the PWM circuit; an output circuit operating at a supply voltage, configured to generate the output signal responding to the PWM signal; and a supply voltage filter, configured to monitor the supply voltage to generate a filtered signal to the summing circuit. The summing circuit is configured to sum the output of the loop filter and the filtered signal to adjust a common-mode level of the input of the PWM circuit.