公开(公告)号：US06191618B1

公开(公告)日：2001-02-20

申请号：US09360110

申请日：1999-07-23

申请人： Eric Gayles ,  Bharat Bhushan ,  Debashree Ghosh

发明人： Eric Gayles ,  Bharat Bhushan ,  Debashree Ghosh

IPC分类号： H03K19096

CPC分类号： H03K19/0963

摘要： A domino logic circuit includes a first domino gate that evaluates one or more inputs responsive to a clock signal, a reset gate, and a second domino gate having a first input coupled to the output of the first domino gate. A first input of a reset gate is coupled to the output of the first domino gate, with a second input of the reset gate being coupled to the output of the second domino gate. The reset gate outputs a precharge signal coupled to a second input of the second domino gate when the second domino gate is discharged and the output of the first domino gate changes state such that a high-to-low transition occurs at the first input of the second domino gate.

摘要翻译： 多米诺骨牌逻辑电路包括：第一多米诺牌，其响应于时钟信号，复位门和第二多米诺牌，评估一个或多个输入，其具有耦合到第一多米诺式门的输出的第一输入。 复位门的第一输入端耦合到第一多米诺门的输出，复位门的第二输入耦合到第二多米诺门的输出端。 当第二多米诺式门被放电并且第一多米诺式门的输出改变状态时，复位门输出耦合到第二多米诺门的第二输入的预充电信号，使得在第一输入端发生高到低的转换 第二个多米诺骨牌门