公开(公告)号：US07290117B2

公开(公告)日：2007-10-30

申请号：US10032109

申请日：2001-12-20

申请人： Erik E. Erlandson ,  David A. Tremblay, Jr.

发明人： Erik E. Erlandson ,  David A. Tremblay, Jr.

IPC分类号： G06F12/00 ,  G06F8/00

CPC分类号： G11C7/1021 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes, and the comparator compares the external address to a value. Based on the relationship between the external address and the value, the comparator enables or disables the data transfer. For example, such a memory can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address. Or, the comparator can compare the external or internal address to a predetermined end address, and the memory can terminate the cycle when the external or internal address equals the end address.

摘要翻译： 存储器包括地址总线，地址计数器，地址解码器，比较器和控制电路。 在数据读或写周期期间，地址总线接收外部地址，地址计数器产生一个内部地址，地址解码器解码，比较器将外部地址与一个值进行比较。 基于外部地址和值之间的关系，比较器启用或禁用数据传输。 例如，这样的存储器可以通过确定当前外部列地址何时不再等于当前内部列地址来终止页模式读/写周期。 这允许系统通过将外部列地址设置为不等于内部列地址的值来在预定数量的数据传输之后终止循环。 或者，比较器可以将外部或内部地址与预定的结束地址进行比较，并且当外部或内部地址等于结束地址时，存储器可以终止循环。