Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree
    1.
    发明授权
    Method and apparatus for de-skewing a clock using a first and second phase locked loop and a clock tree 有权
    使用第一和第二锁相环和时钟树对时钟进行去偏转的方法和装置

    公开(公告)号:US06810486B2

    公开(公告)日:2004-10-26

    申请号:US09818614

    申请日:2001-03-28

    IPC分类号: G06F104

    CPC分类号: G06F1/10

    摘要: A technique for de-skewing second and third clocks with respect to a first clock includes receiving the first clock and generating a fourth clock from the first and second clocks. A fifth clock and the third clock are generated from the fourth clock, the fifth clock being substantially identical to the third clock. The second clock is then generated from the fifth clock. The fourth clock is generated by a first phase locked loop having the first and second clocks as its inputs and the second clock is generated by a second phase locked loop connected to a clock tree, the second phase locked loop having the fifth clock and the second clock as its inputs.

    摘要翻译: 用于相对于第一时钟去偏斜第二和第三时钟的技术包括接收第一时钟并从第一和第二时钟产生第四时钟。 从第四时钟产生第五时钟和第三时钟,第五时钟与第三时钟基本相同。 然后从第五个时钟产生第二个时钟。 所述第四时钟由具有所述第一和第二时钟作为其输入的第一锁相环生成,所述第二时钟由连接到时钟树的第二锁相环产生,所述第二锁相环具有所述第五时钟和所述第二时钟 时钟作为其输入。

    Tracking bin split technique
    2.
    发明授权

    公开(公告)号:US06654899B2

    公开(公告)日:2003-11-25

    申请号:US09818615

    申请日:2001-03-28

    IPC分类号: G06F300

    CPC分类号: H03L7/23 G06F1/04

    摘要: A tracking bin split technique includes: receiving an externally generated board clock and selectively generating a reference clock in phase with the externally generated board clock at a frequency equal to that of the externally generated board clock multiplied by M, wherein M is an integer equal to or greater than one; receiving the reference clock output by the clock generator and generating an output clock with a phase locked loop in phase with the reference clock and having a frequency which is an integral multiple of that of the reference clock; and receiving the output clock generated by the phase locked loop and generating a feedback clock for the phase locked loop in phase with the output clock and at a frequency equal to that of the output clock divided by 2N, wherein 2N is an even integer equal to or greater than two.