公开(公告)号：US11775003B2

公开(公告)日：2023-10-03

申请号：US17565503

申请日：2021-12-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain ,  Chi-Yeu Chao

IPC: G06F1/12 ,  G06F1/10 ,  G06F1/08

CPC classification number: G06F1/10 ,  G06F1/08 ,  G06F1/12

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

公开(公告)号：US10749508B1

公开(公告)日：2020-08-18

申请号：US16525686

申请日：2019-07-30

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain

IPC: H03K5/04 ,  H03K3/017 ,  H03K3/356

Abstract: A signal converter, a duty-cycle corrector, and a differential clock generator are provided. The differential clock generator includes the signal converter and the duty-cycle corrector. The signal converter is capable of calibrating skew distortion, and the duty-cycle corrector is capable of calibrating duty-cycle distortion. With the signal converter and the duty-cycle corrector, the differential clock generator can be applied to communication devices operating at high frequency.

公开(公告)号：US11831349B2

公开(公告)日：2023-11-28

申请号：US17575664

申请日：2022-01-14

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain

IPC: H04B1/10 ,  H03K19/20 ,  H03K5/24

CPC classification number: H04B1/1018 ,  H03K5/24 ,  H03K19/20

Abstract: A serial signal detector and a differential signal detection method are provided. The serial signal detector includes a voltage comparison module and a hybrid logic filter. The voltage comparison module receives a differential signal, including a first shifted signal and a second shifted signal. The voltage comparison module includes a first comparator and a second comparator. Based on the first shifted signal, the second shifted signal, and a voltage threshold, the first and the second comparators respectively generate a first and a second comparison signals. The hybrid logic filter includes a controllable logic gate and a capacitor. The controllable logic gate performs a logic operation related to the first and the second comparison signals and generates a filtered and converted pulse accordingly. The controllable logic gate and the capacitor jointly perform a preliminary filtering operation to the filtered and converted pulse while the logic operation is being performed.

公开(公告)号：US10797683B1

公开(公告)日：2020-10-06

申请号：US16811371

申请日：2020-03-06

Applicant: FARADAY TECHNOLOGY CORPORATION

Inventor： Vinod Kumar Jain ,  Chi-Yeu Chao ,  Prateek Kumar Goyal ,  Han-Kyul Lim

IPC: H03K3/017 ,  H03K5/156 ,  G06F1/04

Abstract: A calibration circuit, including a duty cycle correction circuit and a phase correction circuit and associated calibrating method, are provided. Firstly, a first duty cycle adjusted clock and a second duty cycle adjusted clock are generated by the duty cycle correction circuit based on a first input clock and a second input clock, respectively. Then, a first delay adjusted clock and a second delay adjusted clock are generated by the phase correction circuit based on a phase of the first duty cycle adjusted clock, and a detection signal is generated. The detection signal is related to a duty cycle of the first input clock, a duty cycle of the second input clock, and a phase difference between the second delay adjusted clock and the first delay adjusted clock. Later, the duty cycle correction circuit and the phase correction circuit are controlled in response to the detection signal.