公开(公告)号：US20180024951A1

公开(公告)日：2018-01-25

申请号：US15213875

申请日：2016-07-19

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Graham Edmiston

IPC: G06F13/28 ,  G06F9/50 ,  G06F9/48 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F9/4881

Abstract: A heterogeneous multi-processor device having a first processor component arranged to issue a data access command request, a second processor component arranged to execute a set of threads, a task scheduling component arranged to schedule the execution of threads by the second processor component, and an internal memory component. In response to the data access command request being issued by the first processor component, the task scheduling component is arranged to wait for activities relating to the indicated subset of threads to finish, and when the activities relating to the indicated subset of threads have finished to load a command thread for execution by the second processor component, the command thread being arranged to cause the second processor component to read the indicated data from the at least one region of memory and make the read data available to the first processor component.