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公开(公告)号:US12266412B2
公开(公告)日:2025-04-01
申请号:US18323430
申请日:2023-05-25
Applicant: Faraday Technology Corp.
Inventor: Yi-Hsin Tseng , Chi-Chang Shuai , Yen-Yao Wang
Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.
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公开(公告)号:US20240355408A1
公开(公告)日:2024-10-24
申请号:US18323430
申请日:2023-05-25
Applicant: Faraday Technology Corp.
Inventor: Yi-Hsin Tseng , Chi-Chang Shuai , Yen-Yao Wang
CPC classification number: G11C29/4401 , G11C15/04
Abstract: A content addressable memory (CAM) and a CAM cell are provided. The CAM includes a memory cell array and a disabling circuit. The memory cell array includes a plurality of CAM cells, wherein each of the CAM cells includes a memory cell circuit and a comparison circuit. When the CAM cells in a first column of the memory cell array are normal, the disabling circuit enables the comparison circuits of the CAM cells in the first column, so that the comparison circuits in the first column respectively present the comparison results on different match lines. When any one of the CAM cells in the first column is defective, the disabling circuit disables the comparison circuits of the CAM cells in the first column, so that the disabled comparison circuits does not affect the different match lines.
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