公开(公告)号：US06353843B1

公开(公告)日：2002-03-05

申请号：US09415485

申请日：1999-10-08

申请人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir A. Farooqui

发明人： Farzad Chehrazi ,  Vojin G. Oklobdzija ,  Aamir A. Farooqui

IPC分类号： G06F752

CPC分类号： G06F7/5324 ,  G06F7/49994 ,  G06F7/5338 ,  G06F2207/382

摘要： A partitioned multiplier circuit which is designed for high speed operations. The multiplier of the present invention can perform one 32×32 bit multiplication, two 16×16 bit multiplications (simultaneously) or four 8×8 bit multiplications (simultaneously) depending on input partitioning signals. The time required to perform either the 32×32 bit or the 16×16 bit or the 8×8 bit multiplications is constant. Therefore, multiplication results are available with a constant latency regardless of operand bit-size. In one embodiment, the latency is two clock cycles but the multiplier circuit has a throughput of one clock cycle due to pipelining. The input operands can be signed or unsigned. The hardware is partitioned without any significant increase in the delay or area and the multiplier can provide six different modes of operation. In one embodiment, Booth encoding is used for the generation of 17 partial products which are compressed using a compression tree into two 64-bit values. This is performed in the first pipeline stage to generate a sum and a carry vector. These values are then added, in the second pipestage, using a carry propagate adder circuit to provide a single 64-bit result. In the case of 16×16 bit multiplication, the 64-bit result contains two 32-bit results. In the case of 8×8 bit multiplication, the 64-bit result contains four 16-bit results. Due to its high operating speed, the multiplier circuit is advantageous for use in multi-media applications, such as audio/visual rendering and playback.

摘要翻译： 分频乘法电路，专为高速运行而设计。 根据输入的分频信号，本发明的乘法器可以执行一个32×32位乘法，两次16×16位乘法（同时）或四个8×8位乘法（同时）。 执行32x32位或16x16位或8x8位乘法所需的时间是常数。 因此，无论操作数位大小如何，乘法结果都可以使用恒定的延迟。 在一个实施例中，等待时间是两个时钟周期，但乘法器电路由于流水线而具有一个时钟周期的吞吐量。 输入操作数可以是有符号的或无符号的。 硬件被分配，而延迟或区域没有任何显着增加，乘法器可以提供六种不同的操作模式。 在一个实施例中，布斯编码用于生成使用压缩树压缩为两个64位值的17个部分乘积。 这在第一流水线阶段执行以产生和和进位向量。 然后，在第二个管道中，使用进位传播加法器电路来添加这些值，以提供单个64位结果。 在16×16位乘法的情况下，64位结果包含两个32位结果。 在8×8位乘法的情况下，64位结果包含四个16位结果。 由于其高的操作速度，乘法器电路有利于在多媒体应用中使用，例如音频/视觉呈现和回放。

公开(公告)号：US20080288728A1

公开(公告)日：2008-11-20

申请号：US12122900

申请日：2008-05-19

申请人： Aamir A. Farooqui ,  Saima A. Farooqui ,  Rajeev Huralikoppi

发明人： Aamir A. Farooqui ,  Saima A. Farooqui ,  Rajeev Huralikoppi

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F12/00

CPC分类号： G06F15/786 ,  G06F9/30036 ,  G06F9/30101 ,  Y02D10/13

摘要： A media signal processor (MSP) architecture is disclosed in this invention To address the shortcomings of conventional high performance processing units, the MSP architecture is designed using a new concept in parallel processing—“Same Instruction Different Operation” (SIDO) and “Same Instruction Multiple Data” (SIMD) architectures. The scalable nature of the architecture makes it possible to add multiple cores to match the processing needs of any type of data processing application. With multiple MSPs working in parallel, multiple data streams can be processed in either parallel or in a sequentially pipelined manner, using a software-based control mechanism.

摘要翻译： 在本发明中公开了一种媒体信号处理器（MSP）架构为了解决传统的高性能处理单元的缺点，MSP体系结构使用并行处理中的新概念 - “相同指令不同操作”（SIDO）和“相同指令 多数据“（SIMD）架构。 架构的可扩展性使得可以添加多个内核以匹配任何类型的数据处理应用程序的处理需求。 使用多个MSP并行工作，可以使用基于软件的控制机制来并行或以顺序流水线的方式处理多个数据流。

公开(公告)号：US20090031117A1

公开(公告)日：2009-01-29

申请号：US12016171

申请日：2008-06-16

申请人： Aamir A. Farooqui ,  Saima A. Farooqui

发明人： Aamir A. Farooqui ,  Saima A. Farooqui

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30181

摘要： A same instruction different operation (SIDO) processor is disclosed in which the instruction control word is supplied using data bus as one operand and the data to be operated is supplied through another operand. Also disclosed is a method for the provision of operation-code along with data/operands using a short instruction word. With all the execution units working in parallel on multiple data operands, a variety of operations can be performed in parallel. This allows short instruction format and flexibility to dynamically program the processor on the fly by changing data/operand words, and supports basic integer operations using very simple and efficient hardware execution units.

摘要翻译： 公开了相同的指令不同操作（SIDO）处理器，其中使用数据总线作为一个操作数提供指令控制字，并且通过另一个操作数提供要被操作的数据。 还公开了一种使用短指令字与数据/操作数一起提供操作码的方法。 随着所有执行单元在多个数据操作数上并行工作，可以并行执行各种操作。 这允许短指令格式和灵活性通过更改数据/操作数字来动态编程处理器，并且使用非常简单和高效的硬件执行单元来支持基本整数运算。