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公开(公告)号：US06243728B1
公开(公告)日：2001-06-05
申请号：US09351273
申请日：1999-07-12
IPC分类号： G06F501
CPC分类号： G06F7/505 , G06F5/015 , G06F7/49947 , G06F7/49952
摘要： A partitioned shift right logic circuit that is programmable and contains rounding support. The circuit of the present invention accepts a 32-bit value and a shift amount and then performs a right shift operation on the 32-bits and automatically rounds the result(s). Signed or unsigned values can be accepted. The right shift circuit is partitioned so that the 32-bit value can represent: (1) a single 32-bit number; or (2) two 16-bit values. A 1 bit selection input indicates the particular partition format. In operation, if the input value is not negative, then one (“1”) is added at the guard bit position and a right shift with truncate is performed. If the input is negative and the guard bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is zero, then no addition is done and a right shift with truncate is performed. If the input is negative and the guard bit is one and the sticky bit is one, then one is added at the guard bit position and a right shift with truncate is performed. The shift circuitry used by the present invention is fully partitioned to accept word or half-word input and contains multiple cascaded multiplexer stages for performing partitioned right shifting and supports signed shifting. Each multiplexer stage can be programmed to perform a selected shift amount (including 0 shift). The right shift circuit of the present invention can be used in multi-media applications and can also be used for general purpose and VLIW (very long instruction word) processor without performance degradation.
摘要翻译： 分配的右移逻辑电路，可编程并包含四舍五入支持。 本发明的电路接受32位值和移位量，然后对32位执行右移操作，并自动舍入结果。 可以接受签名或无符号值。 右移位电路被分区，使得32位值可以表示为：（1）单个32位数; 或（2）两个16位值。 1位选择输入表示特定的分区格式。 在操作中，如果输入值不为负，则在保护位位置添加一个（“1”），并执行具有截断的右移位。 如果输入为负并且保护位为零，则不进行任何加法，并且执行具有截断的右移位。 如果输入为负，保护位为1，粘滞位为零，则不进行加法，并执行带截断的右移位。 如果输入为负并且保护位为1，粘滞位为1，则在保护位位置添加一个，并执行带有截断的右移位。 本发明使用的移位电路被完全划分为接受字或半字输入，并且包含用于执行分区右移的多个级联多路复用器级并且支持符号移位。 每个复用器级可以被编程以执行所选择的移位量（包括0移位）。 本发明的右移位电路可用于多媒体应用，也可用于通用和VLIW（非常长的指令字）处理器，而不会降低性能。
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公开(公告)号：US06301599B1
公开(公告)日：2001-10-09
申请号：US09280176
申请日：1999-03-29
IPC分类号： G06F752
CPC分类号： G06F7/5338
摘要： An improved Booth encoder/selector circuit having an optimized critical path. The Booth encoder has a number of inverters coupled to several of the input multiplier bits. The inverted/non-inverted multiplier bits are then fed as inputs to NAND gates as well as a series of pass gates. The outputs of the pass gates are then fed as inputs to other NAND gates. The output from the NAND gates serve as control signals for controlling the Booth selector. The Booth selector is comprised of inverters and pass gates. Multiplicand bits are input to the pass gates. The control signals generated by the Booth encoder are selectively coupled to the inverters and pass gates such that they control which one of a plurality of multiplicand bits are selected for output. Basically, the Booth selector functions as a multiplexer whereby one of the following is output: the multiplicand bit is multiplied by zero, multiplied by one, multiplied by negative one, multiplied by two, or multiplied by negative two. The Booth encoder/selector is used in a multiplier circuit to minimize the number of partial products. An adder is then used to sum all of the partial products to arrive at the final answer. In the present invention, the critical path has been optimized such that the overall speed of the multiplier is greatly improved.
摘要翻译： 具有优化的关键路径的改进的布斯编码器/选择器电路。 布斯编码器具有耦合到多个输入乘法器位的多个反相器。 然后将反相/非反相乘法器位作为输入馈送到NAND门以及一系列通路。 然后将通过栅极的输出作为输入馈送到其他NAND门。 来自NAND门的输出用作控制Booth选择器的控制信号。 展位选择器由逆变器和通过门组成。 乘数位被输入到通过门。 由布斯编码器产生的控制信号选择性地耦合到反相器并传递门，使得它们控制多个被乘数位中的哪一个被选择用于输出。 基本上，展位选择器用作多路复用器，其中输出以下之一：被乘数位乘以零乘以1，乘以负1乘以2乘以乘以2。 Booth编码器/选择器用于乘法器电路中以最小化部分乘积的数量。 然后使用加法器来求出所有部分乘积以得出最终答案。 在本发明中，关键路径已被优化，使得乘法器的总体速度大大提高。
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