公开(公告)号：US07454729B1

公开(公告)日：2008-11-18

申请号：US11281178

申请日：2005-11-16

申请人： Fiyaz Kanji ,  Albert Chang

发明人： Fiyaz Kanji ,  Albert Chang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/84

摘要： A method for validating timing violations in a testbench is provided. The method includes obtaining the timing requirements for a design under test from a first file. The timing requirements for the design may be entered as an input to a verification tool. Then, based on the timing requirements of the user, a place and route operation is performed resulting in a design layout. Following the place and route operation, timing results are obtained for the design layout. The timing results may be obtained through simulation. From the timing results, timing values are extracted at the input level so that the inputs may be driven based on those timing values. The timing values compensate for any timing violations that may have resulted from the timing models of the verification tool.

摘要翻译： 提供了一种用于验证测试台中的定时违规的方法。 该方法包括从第一个文件获得被测设计的时序要求。 设计的时序要求可以作为验证工具的输入输入。 然后，基于用户的定时要求，执行位置和路线操作，导致设计布局。 在位置和路线操作之后，获得设计布局的定时结果。 定时结果可以通过仿真获得。 从定时结果，在输入电平提取定时值，以便可以基于这些定时值来驱动输入。 定时值补偿了验证工具的时序模型可能导致的任何定时违规。