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公开(公告)号：US4394543A
公开(公告)日：1983-07-19
申请号：US270507
申请日：1981-06-04
CPC分类号： H04M3/301
摘要： A telephone line holding circuit is disclosed which is adapted for temporary connection across a telephone line to maintain that line in a hold condition while line measurements and tests are being performed. The holding circuit is designed to be used over a wide range of line supply voltages and line resistances without introducing line measurement errors. The holding circuit includes a current regulator which maintains the line current at a predetermined level as long as the voltage appearing across the line remains above a predetermined voltage level. The holding circuit also includes a voltage regulator which reduces the predetermined current level to a value which prevents the average line voltage from being reduced below the predetermined voltage level. The holding circuit further includes circuit elements for protecting the circuit elements from damage caused by the application of excessive voltage on the line.
摘要翻译： 公开了一种电话线路保持电路，其适于在电话线路上进行临时连接，以便在进行线路测量和测试时将该线路保持在保持状态。 保持电路设计用于广泛的线路电源电压和线路电阻，而不会引入线路测量误差。 保持电路包括电流调节器，其将线电流维持在预定电平，只要跨过线路出现的电压保持高于预定电压电平即可。 保持电路还包括电压调节器，其将预定电流电平减小到防止平均线路电压降低到低于预定电压电平的值。 保持电路还包括电路元件，用于保护电路元件免受在线路上施加过大电压引起的损坏。
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公开(公告)号：US4468787A
公开(公告)日：1984-08-28
申请号：US319632
申请日：1981-11-09
CPC分类号： H04L1/247 , H04L25/4925
摘要： A source of a duobinary data signal is connected to a remote point by a coupling network having a high pass characteristic and transmission line. The data signal received at the remote point is subtracted from a delayed version thereof to derive the change representative signal, which is utilized at the remote point to regenerate and/or detect code violations of the data signal. Preferably, the received data signal is subtracted from a version thereof delayed by one bit time period. Circuitry generates an indication of a violation when, after assuming one extreme level in a given bit time period, the change representative signal again assumes the same level before assuming the other extreme level during a bit time period separated by an odd number of bit time periods from the given bit time period. Circuitry may also convert the change representative signal back to the duobinary data signal. Specifically, a three-state reversible binary counter is stepped up one state each time the change representative signal assumes its high level, is stepped down one state each time the change representative signal assumes its low level, and remains unchanged in state each time the change representative signal assumes its intermediate level.
摘要翻译： 双二进制数据信号的源通过具有高通特性和传输线的耦合网络连接到远程点。 从远程点接收的数据信号从其延迟版本中减去，以导出在远程点利用的更改代表信号，以再生和/或检测数据信号的代码违例。 优选地，从延迟一位时间段的版本中减去接收的数据信号。 电路产生违规的指示，当在给定位时间周期内假定一个极端电平之后，在由奇数位位时间间隔分开的位时间段期间，在改变代表信号再次假设相同电平之前，假设另一极值电平 从给定的位时间段。 电路还可以将改变代表信号转换回二进制数据信号。 具体地说，每当变化代表信号呈现高电平时，三态可逆二进制计数器被升高一个状态，每当变化代表信号呈现低电平时逐步降低一个状态，并且每当改变状态保持不变状态 代表信号呈现其中间水平。
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3.发明授权
公开(公告)号：US4953181A
公开(公告)日：1990-08-28
申请号：US320587
申请日：1989-03-08
IPC分类号： H04L1/20
CPC分类号： H04L1/205
摘要： Phase slippage of a test clock signal and the direction of such slippage are digitally detected, accumulated, and displayed and/or recorded. A test clock signal is recovered from one digital carrier signal. A reference clock signal is recovered from another digital carrier signal. From the test clock signal, first and second binary signals are generated at a frequency phase synchronized to the test clock signal. The second signal is shifted in phase from the first signal. Responsive to the reference clock signal, the states of the first and second signals are repeatedly sampled such that the sampled states are representative of the phase relationship between the test clock signal and the reference clock signal. Successive samples of the states of the first and second signals are compared to detect unit interval phase shifts between the test clock signal and the reference clock signal. The phase shifts detected by the comparison are accumulated at successive samples are compared to represent phase slippage. An annular display of lamps that facilitates observation of the accumulated slippage.
摘要翻译： 测试时钟信号的相位滑移和这种滑动的方向被数字检测，累加，显示和/或记录。 从一个数字载波信号恢复测试时钟信号。 从另一数字载波信号恢复参考时钟信号。 从测试时钟信号，以与测试时钟信号同步的频率相位产生第一和第二二进制信号。 第二信号从第一信号相位移位。 响应于参考时钟信号，重复采样第一和第二信号的状态，使得采样状态表示测试时钟信号和参考时钟信号之间的相位关系。 将第一和第二信号的状态的连续样本进行比较，以检测测试时钟信号和参考时钟信号之间的单位间隔相移。 比较中检测到的相移在相继的采样点进行比较，以表示相位滑移。 灯的环形显示器，有助于观察累积的滑动。
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4.发明授权
公开(公告)号：US4821287A
公开(公告)日：1989-04-11
申请号：US111775
申请日：1987-10-21
CPC分类号： H04L1/205
摘要： Phase slippage of a test clock signal and the direction of such slippage are digitally detected, accumulated, and displayed and/or recorded. A test clock signal is recovered from one digital carrier signal. A reference clock signal is recovered from another digital carrier signal. From the test clock signal, first and second binary signals are generated at a frequency phase synchronized to the test clock signal. The second signal is shifted in phase from the first signal. Responsive to the reference clock signal, the states of the first and second signals are repeatedly sampled such that the sampled states are representative of the phase relationship between the test clock signal and the reference clock signal. Successive samples of the states of the first and second signals are compared to detect unit interval phase shifts between the test clock signal and the reference clock signal. The phase shifts detected by the comparison are accumulated at successive samples are compared to represent phase slippage. An annular display of lamps that facilitates observation of the accumulated slippage.
摘要翻译： 测试时钟信号的相位滑移和这种滑动的方向被数字检测，累加，显示和/或记录。 从一个数字载波信号恢复测试时钟信号。 从另一数字载波信号恢复参考时钟信号。 从测试时钟信号，以与测试时钟信号同步的频率相位产生第一和第二二进制信号。 第二信号从第一信号相位移位。 响应于参考时钟信号，重复采样第一和第二信号的状态，使得采样状态表示测试时钟信号和参考时钟信号之间的相位关系。 将第一和第二信号的状态的连续样本进行比较，以检测测试时钟信号和参考时钟信号之间的单位间隔相移。 比较中检测到的相移在相继的采样点进行比较，以表示相位滑移。 灯的环形显示器，有助于观察累积的滑动。
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