公开(公告)号：US20120173943A1

公开(公告)日：2012-07-05

申请号：US13340560

申请日：2011-12-29

申请人： Franco CESARI

发明人： Franco CESARI

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/3177 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318552 ,  G01R31/318594

摘要： An embodiment is directed to extended test coverage of complex multi-clock-domain integrated circuits without forgoing a structured and repeatable standard approach, thus avoiding custom solutions and freeing the designer to implement his RTL code, respecting only generally few mandatory rules identified by the DFT engineer. Such an embodiment is achieved by introducing in the test circuit an embodiment of an additional functional logic circuit block, named “inter-domain on chip clock controller” (icOCC), interfaced with every suitably adapted clock-gating circuit (OCC), of the different clock domains. The icOCC actuates synchronization among the different OCCs that source the test clock signals coming from an external ATE or ATPG tool and from internal at-speed test clock generators to the respective circuitries of the distinct clock domains. Scan structures like the OCCs, scan chain, etc., may be instantiated at gate pre-scan level, with low impact onto the functional RTL code written by the designer.

摘要翻译： 一个实施例涉及复杂多时钟域集成电路的扩展测试覆盖，而不需要结构化和可重复的标准方法，因此避免了定制解决方案并释放设计者来实现他的RTL代码，仅仅遵循由DFT识别的一般强制规则 工程师。 这种实施例通过在测试电路中引入与每个适当适配的时钟门控电路（OCC）接口的附加功能逻辑电路块（称为“片上时钟控制器”（icOCC））的实施例， 不同的时钟域。 icOCC启动不同OCC之间的同步，它们将来自外部ATE或ATPG工具的测试时钟信号和从内部at速度测试时钟发生器输出到不同时钟域的相应电路。 诸如OCC，扫描链等的扫描结构可以在门预扫描级别实例化，对由设计者编写的功能RTL代码具有低影响。