公开(公告)号：US3371281A

公开(公告)日：1968-02-27

申请号：US31856963

申请日：1963-10-24

Applicant: GEN ELECTRIC

Inventor： POWELL NOBLE R

IPC: H03D3/24

CPC classification number: H03D3/242

公开(公告)号：US3914590A

公开(公告)日：1975-10-21

申请号：US52054274

申请日：1974-11-04

Applicant: GEN ELECTRIC

Inventor： IRWIN JOHN M ,  POWELL NOBLE R

IPC: G06F7/48 ,  G06F5/02 ,  H03K13/25

CPC classification number: G06F7/48

Abstract: The present invention relates to a serial two''s complementer whose logical design, by the preferential use of NAND devices and other measures, provides a minimum geometry configuration, in an implementation using metal oxide semiconductor field effect transistors with large scale integration. The two''s complement function is achieved by a binary storage element implemented by an inverter, two NAND gates with two half bit dynamic delays and by an exclusive NOR gate implemented by a NAND gate and a composite NAND-OR configuration. The binary storage element and exclusive NOR gate are interconnected to invert the serial bit stream after the occurrence of the first one to produce the two''s complement.

Abstract translation: 本发明涉及一种串行二进制补码器，其逻辑设计通过优先使用NAND器件和其他措施，在使用具有大规模集成的金属氧化物半导体场效应晶体管的实现中提供最小几何配置。 二进制补码功能由二进制存储元件实现，该二进制存储元件由逆变器，具有两个半位动态延迟的两个NAND门和由NAND门和复合NAND或配置实现的异或门相结合。 二进制存储元件和异或门互相互连，以在第一个存储元件出现之后反转串行比特流以产生二进制补码。