公开(公告)号：US20140154854A1

公开(公告)日：2014-06-05

申请号：US14027837

申请日：2013-09-16

Applicant: Globalfoundries, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/8234

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。

公开(公告)号：US09136175B2

公开(公告)日：2015-09-15

申请号：US14027837

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Peter Baars ,  Erik P. Geiss

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L21/823418 ,  H01L21/76224 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods are provided for fabricating integrated circuits. One method includes etching a plurality of trenches into a silicon substrate and filling the trenches with an insulating material to delineate a plurality of spaced apart silicon fins. A layer of undoped silicon is epitaxially grown to form an upper, undoped region of the fins. Dummy gate structures are formed overlying and transverse to the plurality of fins and a back fill material fills between the dummy gate structures. The dummy gate structures are removed to expose a portion of the fins and a high-k dielectric material and a work function determining gate electrode material are deposited overlying the portion of the fins. The back fill material is removed to expose a second portion and metal silicide contacts are formed on the second portion. Conductive contacts are then formed to the work function determining material and to the metal silicide.

Abstract translation: 提供了用于制造集成电路的方法。 一种方法包括将多个沟槽蚀刻成硅衬底并用绝缘材料填充沟槽以描绘多个间隔开的硅片。 外延生长一层未掺杂的硅以形成翅片的上部未掺杂区域。 虚拟门结构形成为覆盖并横向于多个翅片，并且后填充材料填充在虚拟栅极结构之间。 去除虚拟栅极结构以暴露一部分散热片，并且将高k电介质材料和确定栅极电极材料的功函数沉积在鳍片的该部分上。 去除后填充材料以暴露第二部分，并且在第二部分上形成金属硅化物接触。 然后，将导电触点形成到功函数确定材料和金属硅化物。