公开(公告)号：US20170352661A1

公开(公告)日：2017-12-07

申请号：US15174273

申请日：2016-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo CHENG ,  Carl J. RADENS

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/7848

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to segmented or cut finFET structures and methods of manufacture. The structure includes at least one logic finFET device having a fin of a first length, and at least one memory finFET device having a fin of a second length. The second length is shorter than the first length.

公开(公告)号：US20170352591A1

公开(公告)日：2017-12-07

申请号：US15653127

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. ZHANG ,  Carl J. RADENS ,  Lawrence A. CLEVENGER

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/76808 ,  H01L21/76816

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.