Method, apparatus, and system for improved gate connections on isolation structures in FinFET devices

    公开(公告)号:US10707207B1

    公开(公告)日:2020-07-07

    申请号:US16277496

    申请日:2019-02-15

    Inventor: Hui Zang Dali Shao

    Abstract: A semiconductor device, comprising first and second sets of fins; first and second gate electrodes; first and second isolation structures each separating one of the gate electrodes into a first portion and a second portion; and first and second conductive structures wider than the corresponding isolation structure and disposed on an entirety of a top of the corresponding isolation structure and on a part of the top of each of the first and second portions of the corresponding gate electrode. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device. The semiconductor device may have a low parasitic capacitance and high chip performance.

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