公开(公告)号：US10211168B1

公开(公告)日：2019-02-19

申请号：US15841372

申请日：2017-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Krishna M. Chavali ,  Chien-Hsin Lee ,  Mahadeva Iyer Natarajan

IPC: H01L23/52 ,  H01L23/60 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66 ,  H01L23/528

Abstract: Methods form integrated circuit structures that include a device layer having electronic devices on a substrate, and a multi-layer interconnect structure connected to the device layer. The multi-layer interconnect structure includes alternating insulator layers and wiring layers, power and ground wiring in the wiring layers, non-functional wiring in the wiring layers called dummy fill, and conductive vias extending through the insulator layers. The conductive vias connect the power and ground wiring in the wiring layers to the electronic devices in the device layer. The non-functional wiring is insulated from the power wiring in the wiring layer, and from the electronic devices in the device layer. The conductive vias connect the non-functional wiring (the dummy fill) in the wiring layers through the substrate, or a ground bus, thereby continuously removing static charge that would otherwise accumulate during manufacturing processes.