Chamfering for stress reduction on passivation layer

    公开(公告)号:US10170439B1

    公开(公告)日:2019-01-01

    申请号:US15719861

    申请日:2017-09-29

    Abstract: Devices are formed to have inner layers that have electronic devices, and an outer passivation layer. A patterned conductor is formed on a first surface of the inner layers, and through conductors (that extend through interior insulator layers) are positioned to electrically connect the patterned conductor to the electronic devices. The patterned conductor includes a pattern of connected linear sections that are parallel to the first surface of the inner layers. The linear sections of the patterned conductor meet at conductor corners, and at least one of the conductor corners of the patterned conductor includes a chamfer side that terminates at the linear sections. Further, the chamfer side is not perfectly diagonal, but instead forms unequal angles with the linear sections that intersect to form the corner.

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