公开(公告)号：US20180197734A1

公开(公告)日：2018-07-12

申请号：US15405026

申请日：2017-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bhupesh CHANDRA ,  Annie LEVESQUE ,  Matthew W. STOKER ,  Shreesh NARASIMHA ,  Viorel ONTALUS ,  Michael STEIGERWALT ,  Joshua BELL

IPC: H01L21/02 ,  H01L29/66

CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/7848

Abstract: Reducing wormhole formation during n-type transistor fabrication includes providing a starting structure, the starting structure including a semiconductor substrate, a n-type source region and a n-type drain region of a transistor. The method further includes removing a portion of each of the n-type source region and the n-type drain region, the removing creating a source trench and a drain trench, and forming a buffer layer of silicon-based material(s) over the n-type source region and n-type drain region that is sufficiently thick to inhibit interaction between metal contaminants that may be present below surfaces of the n-type source trench and/or the n-type drain trench, and halogens subsequently introduced prior to source and drain formation. A resulting semiconductor structure is also provided.

公开(公告)号：US20180261512A1

公开(公告)日：2018-09-13

申请号：US15451869

申请日：2017-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brian J. GREENE ,  Shreesh NARASIMHA ,  Scott R. STIFFLER

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.