公开(公告)号：US09659835B1

公开(公告)日：2017-05-23

申请号：US15094026

申请日：2016-04-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jeffrey P. Gambino ,  Richard S. Graf ,  Sundeep Mandal

IPC: H01L27/02 ,  H01L23/36 ,  H01L23/367 ,  G06F17/50

CPC classification number: H01L23/3677 ,  G06F17/505 ,  G06F17/5077 ,  G06F2217/80 ,  H01L27/0207

Abstract: A technique for designing an integrated circuit includes placing standard cells across a first surface of a substrate of an integrated circuit (IC) design. At least two unoccupied regions are located across the first surface that do not include standard cells. Aspect ratios for one or more micro fill vias that can be placed in the at least two unoccupied regions are determined. The one or more micro fill vias are placed in the at least two unoccupied regions. Finally, one or more partial thermal vias are placed from a second surface of the integrated circuit, opposite the first surface, to thermally couple the one or more partial thermal vias to the one or more micro fill vias to create thermal paths from the first surface to the second surface.