公开(公告)号：US10147715B2

公开(公告)日：2018-12-04

申请号：US15481202

申请日：2017-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L21/8234 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66 ,  H01L29/78

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

公开(公告)号：US09653454B1

公开(公告)日：2017-05-16

申请号：US15215043

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L21/336 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/823431 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/785

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.