公开(公告)号：US09230637B1

公开(公告)日：2016-01-05

申请号：US14481384

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shahid Ahmad Butt ,  Pamela Castalino ,  Harold Pilo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418

Abstract: Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q′ (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL′ (bit line complement, or “BLC”) line, and the Q′ side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.

Abstract translation: 晶体管连接到SRAM阵列列的外部。 在SRAM单元的Q侧，一个晶体管从VSS连接到地。 在SRAM单元的Q'（Q补码）侧，另一个晶体管从VSS连接到地。 每个晶体管都是互补的位线。 Q侧晶体管由BL'（位线补码或“BLC”）线选通，Q'侧由BL线选通。 在写入操作期间补码侧的接地断开以增加写入操作期间的状态改变的性能，其中将逻辑1写入Q节点，从而提高写入裕度。