公开(公告)号：US09472509B2

公开(公告)日：2016-10-18

申请号：US15152600

申请日：2016-05-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jae Kyu Cho ,  Shan Gao

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/784 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.

Abstract translation: 公开了在半导体晶片上的管芯之间形成虚设金属结构的方法和所得到的器件。 实施例可以包括在多个管芯区域之间形成从半导体晶片的衬底延伸到半导体晶片的顶部金属互连层的金属互连层，每个金属互连层包括多个虚拟垂直互连访问（VIA）和 多个虚拟金属线，多个虚拟金属线横向连接各个金属互连层内的多个伪VIA，以及在第一金属互连层内垂直连接多个虚拟金属线内的虚拟VIA 第一金属互连层连接到第二金属互连层内的多个虚拟金属线，第二金属互连层位于第一金属互连层的下方。

公开(公告)号：US09406608B2

公开(公告)日：2016-08-02

申请号：US14515836

申请日：2014-10-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jae Kyu Cho ,  Shan Gao

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L23/562 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/784 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L23/585 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a dummy metal structure between dies on a semiconductor wafer and the resulting devices are disclosed. Embodiments may include forming metal interconnection layers extending from a substrate of a semiconductor wafer to a top metal interconnection layer of the semiconductor wafer between a plurality of die regions, each of the metal interconnection layers including a plurality of dummy vertical interconnect accesses (VIAs) and a plurality of dummy metal lines, with the plurality of dummy metal lines laterally connecting the plurality of dummy VIAs within each respective metal interconnection layer, and a plurality of dummy VIAs within a first metal interconnection layer vertically connecting a plurality of dummy metal lines within the first metal interconnection layer to a plurality of dummy metal lines within a second metal interconnection layer, and the second metal interconnection layer being below the first metal interconnection layer.