公开(公告)号：US09230913B1

公开(公告)日：2016-01-05

申请号：US14457155

申请日：2014-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Biswanath Senapati ,  Jagar Singh ,  Karthik Chandrasekaran

IPC: H01L21/30 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.

Abstract translation: 提供了使电路结构中的寄生电容最小化的结构和方法。 该结构可以包括支撑一个或多个电路的衬底和在衬底上方的一个或多个金属化层。 金属化层包括由导电填充元件阵列限定的导电图案，其中阵列的导电填充元件是离散的，电隔离的元件，其大小至少部分地满足预定义的最小面积占有率 金属化层的化学机械抛光，并且使金属化层内的寄生电容最小化，以及最小化金属化层和电路之间的寄生电容，以及如果存在多个金属化层，则在层之间。