公开(公告)号：US20150097263A1

公开(公告)日：2015-04-09

申请号：US14045340

申请日：2013-10-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan KIM ,  Jason R. CANTONE ,  Wenhui WANG

IPC: H01L21/74 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L23/528 ,  H01L21/743 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A methodology for forming contact areas by a multiple patterning process that provides increased yield and lower risk of contact-to-contact short at points of tight tip-to-tip spacing and the resulting device are disclosed. Embodiments include forming one or more trench patterning layers on a planarized surface of a wafer, forming one or more trenches in the one or more trench patterning layers, forming a block mask at one or more points along the one or more trenches, extending the one or more trenches down to a substrate level of the wafer, and removing the block mask from the one or more points.

Abstract translation: 公开了一种用于通过多重图案化工艺形成接触面积的方法，其提供增加的产量并且在紧密的尖端到尖端间距的点处产生接触 - 接触短的风险以及所得到的装置。 实施例包括在晶片的平坦化表面上形成一个或多个沟槽图案化层，在一个或多个沟槽图案化层中形成一个或多个沟槽，在沿一个或多个沟槽的一个或多个点处形成阻挡掩模， 或更多的沟槽直到晶片的衬底水平，以及从一个或多个点移除阻挡掩模。

公开(公告)号：US20150097249A1

公开(公告)日：2015-04-09

申请号：US14046351

申请日：2013-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan KIM ,  Jason CANTONE

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/02

CPC classification number: H01L21/823475 ,  H01L27/0207 ,  H01L27/088

Abstract: Methodologies for forming a cross coupling gate and a resulting device are disclosed. Embodiments include: providing a plurality of gates extending vertically on a plurality of equally spaced horizontal positions of an IC; providing a cross-couple region of a gate of the plurality of gates, the cross-couple region including a portion of the gate extending from a first horizontal position of the horizontal positions to a second horizontal position of the horizontal positions; and providing at least one of the plurality of gates with an overlap of first and second segments of the at least one gate, the first and second segments being designated to be decomposed using different colors.

Abstract translation: 公开了用于形成交叉耦合栅极和所得到的器件的方法。 实施例包括：提供在IC的多个等间隔的水平位置上垂直延伸的多个门; 提供多个栅极的栅极的交叉耦合区域，所述交叉耦合区域包括从所述水平位置的第一水平位置延伸到所述水平位置的第二水平位置的所述栅极的一部分; 以及提供所述多个门中的至少一个具有所述至少一个栅极的第一和第二段的重叠，所述第一和第二段被指定为使用不同的颜色分解。