FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS
    1.
    发明申请
    FABRICATING FIELD EFFECT TRANSISTOR(S) WITH STRESSED CHANNEL REGION(S) AND LOW-RESISTANCE SOURCE/DRAIN REGIONS 有权
    具有应力通道区域(S)和低电阻源/漏区的制造场效应晶体管

    公开(公告)号:US20150311120A1

    公开(公告)日:2015-10-29

    申请号:US14262882

    申请日:2014-04-28

    Abstract: Methods of fabricating field effect transistors having a source region and a drain region separated by a channel region are provided which include: using a single mask step in forming a first portion(s) and a second portion(s) of at least one of the source region or the drain region, the first portion(s) including a first material selected and configured to facilitate the first portion(s) stressing the channel region, and the second portion(s) including a second material selected and configured to facilitate the second portion(s) having a lower electrical resistance than the first portion(s). One embodiment includes: providing the first material with a crystal lattice structure; and forming the second material by disposing another material interstitially with respect to the crystal lattice structure. Another embodiment includes forming the first portion and the second portion within at least one of a source cavity or a drain cavity of the semiconductor substrate.

    Abstract translation: 提供了制造具有由沟道区域分隔的源极区域和漏极区域的场效应晶体管的方法,其包括:使用单个掩模步骤来形成第一部分和第二部分中的至少一个 源极区域或漏极区域,第一部分包括被选择并且被配置为便于使第一部分对通道区域施加压力的第一材料,并且第二部分包括选择和构造成促进 第二部分具有比第一部分更低的电阻。 一个实施例包括:为第一材料提供晶格结构; 以及通过相对于所述晶格结构间歇地设置另一材料来形成所述第二材料。 另一实施例包括在半导体衬底的源腔或漏腔中的至少一个中形成第一部分和第二部分。

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