DYNAMIC INTEGRATED CIRCUIT FABRICATION METHODS
    1.
    发明申请
    DYNAMIC INTEGRATED CIRCUIT FABRICATION METHODS 审中-公开
    动态集成电路制造方法

    公开(公告)号:US20160284609A1

    公开(公告)日:2016-09-29

    申请号:US14671265

    申请日:2015-03-27

    CPC classification number: H01L22/20 G01B21/04 G01B21/08 G01B2210/56 H01L22/12

    Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

    Abstract translation: 提供了用于形成具有降低的屈服损失和失效模具的半导体器件的方法和工艺。 一种方法包括,例如:在至少一个制造处理之后获得晶片; 在所述至少一个制造处理之后获取所述晶片的第一r,θ,z测量值; 执行至少一个第二制造处理; 在所述至少一个第二制造处理之后取得所述晶片的第二r,θ,z测量值; 并分析相对于第一个r,θ,z测量的第二个r,θ,z测量。 一种方法包括例如:获得具有衬底的晶片和位于衬底上的至少一个第一器件; 在r,θ,z坐标系中进行第一次测量; 在衬底上形成至少一个第二器件; 在r,θ,z坐标系中进行第二次测量; 以及分析关于第一测量的第二测量。

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