Dynamic integrated circuit fabrication methods

    公开(公告)号:US10103070B2

    公开(公告)日:2018-10-16

    申请号:US14671265

    申请日:2015-03-27

    Abstract: Methods and processes for forming semiconductor devices with reduced yield loss and failed dies are provided. One method includes, for instance: obtaining a wafer after at least one fabrication processing; taking first r, θ, z measurements of the wafer after the at least one fabrication processing; performing at least one second fabrication processing; taking second r, θ, z measurements of the wafer after the at least one second fabrication processing; and analyzing the second r, θ, z measurements with respect to the first r, θ, z measurements. A process includes, for instance: obtaining a wafer with a substrate and at least one first device positioned on the substrate; taking first measurements in a r, θ, z coordinate system; forming at least one second device over the substrate; taking second measurements in the r, θ, z coordinate system; and analyzing the second measurements with respect to the first measurements.

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