公开(公告)号：US20210242230A1

公开(公告)日：2021-08-05

申请号：US16781527

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Faraz KHAN ,  Dan MOY ,  Norman W. ROBSON ,  Robert KATZ ,  Darren L. ANAND ,  Toshiaki KIRIHATA

IPC: H01L27/11568 ,  H01L29/792 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/24

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.