公开(公告)号：US11245032B2

公开(公告)日：2022-02-08

申请号：US16373620

申请日：2019-04-02

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Ignasi Cortes ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi ,  Richard Francis Taylor, III

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.

公开(公告)号：US11929433B2

公开(公告)日：2024-03-12

申请号：US17454481

申请日：2021-11-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ignasi Cortes ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi ,  Richard Francis Taylor, III

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7835 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/78603 ,  H01L29/78624

Abstract: The present disclosure relates generally to semiconductor structures, and more particularly to asymmetric field effect transistors (FET) on fully depleted silicon on insulator (FDSOI) semiconductor devices for high frequency and high voltage applications and their method of manufacture. The semiconductor device of the present disclosure includes a semiconductor-on-insulator (SOI) layer disposed above a substrate, the SOI layer having a source region, a channel region, a drift region and a drain region, where the drift region adjoins the drain region and the channel region, a gate structure disposed on the channel region, a multilayer drain spacer disposed on a drain-facing sidewall of the gate structure and covering the drift region, and a source spacer disposed on a source-facing sidewall of the gate structure, where the source and drain spacers are asymmetric with each other.